linux-stable.git/arch/mips/kernel/cps-vec.S, branch v4.2

MIPS: cps-vec: Use macros for various arithmetics and memory operations

2015-07-09T09:17:01+00:00

Replace lw/sw and various arithmetic instructions with macros so the
code can work on 64-bit kernels as well.

Cc:  # 3.16+
Reviewed-by: Paul Burton 
Signed-off-by: Markos Chandras 
Cc: linux-mips@linux-mips.org
Cc: stable@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/10591/
Signed-off-by: Ralf Baechle

MIPS: kernel: cps-vec: Replace KSEG0 with CKSEG0

2015-07-09T09:15:44+00:00

In preparation for 64-bit CPS support, we replace KSEG0 with CKSEG0
so 64-bit kernels can be supported.

Cc:  # 3.16+
Reviewed-by: Paul Burton 
Signed-off-by: Markos Chandras 
Cc: linux-mips@linux-mips.org
Cc: stable@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/10590/
Signed-off-by: Ralf Baechle

MIPS: kernel: cps-vec: Use ta0-ta3 pseudo-registers for 64-bit

2015-07-09T09:15:17+00:00

The cps-vec code assumes O32 ABI and uses t4-t7 in quite a few places. This
breaks the build on 64-bit. As a result of which, use the pseudo-registers
ta0-ta3 to make the code compatible with 64-bit.

Cc:  # 3.16+
Reviewed-by: Paul Burton 
Signed-off-by: Markos Chandras 
Cc: linux-mips@linux-mips.org
Cc: stable@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/10589/
Signed-off-by: Ralf Baechle

MIPS: kernel: cps-vec: Replace mips32r2 ISA level with mips64r2

2015-07-09T09:14:48+00:00

mips32r2 is a subset of mips64r2, so we replace mips32r2 with mips64r2
in preparation for 64-bit CPS support.

Cc:  # 3.16+
Reviewed-by: Paul Burton 
Signed-off-by: Markos Chandras 
Cc: linux-mips@linux-mips.org
Cc: stable@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/10588/
Signed-off-by: Ralf Baechle

MIPS: kernel: cps-vec: Replace 'la' macro with PTR_LA

2015-07-09T09:13:33+00:00

The PTR_LA macro will pick the correct "la" or "dla" macro to
load an address to a register. This gets rids of the following
warnings (and others) when building a 64-bit CPS kernel:

arch/mips/kernel/cps-vec.S:63: Warning: la used to load 64-bit address
arch/mips/kernel/cps-vec.S:159: Warning: la used to load 64-bit address
arch/mips/kernel/cps-vec.S:220: Warning: la used to load 64-bit address
arch/mips/kernel/cps-vec.S:240: Warning: la used to load 64-bit address
[...]

Cc:  # 3.16+
Reviewed-by: Paul Burton 
Signed-off-by: Markos Chandras 
Cc: linux-mips@linux-mips.org
Cc: stable@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/10587/
Signed-off-by: Ralf Baechle

MIPS: kernel: cps-vec: Replace "addi" with "addiu"

2015-02-17T15:37:28+00:00

The "addi" instruction will trap on overflows which is not something
we need in this code, so we replace that with "addiu".

Link: http://www.linux-mips.org/archives/linux-mips/2015-01/msg00430.html
Cc: Maciej W. Rozycki 
Cc:  # v3.15+
Cc: Paul Burton 
Signed-off-by: Markos Chandras

MIPS: kernel: cps-vec: Set ISA level to mips32r2 for the MIPS MT ASE

2014-11-24T06:44:06+00:00

Fixes the following build warnings:
arch/mips/kernel/cps-vec.S: Assembler messages:
arch/mips/kernel/cps-vec.S:228: Warning: the `mt' extension requires
MIPS32 revision 2 or greater
[...]
arch/mips/kernel/cps-vec.S: Assembler messages:
arch/mips/kernel/cps-vec.S:345: Warning: the `mt' extension requires
MIPS32 revision 2 or greater

Signed-off-by: Markos Chandras 
Cc: Paul Burton 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/7355/
Signed-off-by: Ralf Baechle

MIPS: CPS: Initialize EVA before bringing up VPEs from secondary cores

2014-08-19T16:24:41+00:00

The CPS code is doing several memory loads when configuring the VPEs
from secondary cores, so the segmentation control registers must be
initialized in time otherwise the kernel will crash with strange
TLB exceptions.

Reviewed-by: Paul Burton 
Signed-off-by: Markos Chandras 
Patchwork: http://patchwork.linux-mips.org/patch/7424/
Signed-off-by: James Hogan

MIPS: smp-cps: duplicate core0 CCA on secondary cores

2014-05-28T15:20:33+00:00

Rather than hardcoding CCA=0x5 for secondary cores, re-use the CCA from
the boot CPU. This allows overrides of the CCA using the cca= kernel
parameter to take effect on all CPUs for consistency.

Signed-off-by: Paul Burton

MIPS: pm-cps: add PM state entry code for CPS systems

2014-05-28T15:20:31+00:00

This patch adds code to generate entry & exit code for various low power
states available on systems based around the MIPS Coherent Processing
System architecture (ie. those with a Coherence Manager, Global
Interrupt Controller & for >=CM2 a Cluster Power Controller). States
supported are:

  - Non-coherent wait. This state first leaves the coherent domain and
    then executes a regular MIPS wait instruction. Power savings are
    found from the elimination of coherency interventions between the
    core and any other coherent requestors in the system.

  - Clock gated. This state leaves the coherent domain and then gates
    the clock input to the core. This removes all dynamic power from the
    core but leaves the core at the mercy of another to restart its
    clock. Register state is preserved, but the core can not service
    interrupts whilst its clock is gated.

  - Power gated. This deepest state removes all power input to the core.
    All register state is lost and the core will restart execution from
    its BEV when another core powers it back up. Because register state
    is lost this state requires cooperation with the CONFIG_MIPS_CPS SMP
    implementation in order for the core to exit the state successfully.

The code will detect which states are available on the current system
during boot & generate the entry/exit code for those states. This will
be used by cpuidle & hotplug implementations.

Signed-off-by: Paul Burton