linux-stable.git/arch/mips/include/uapi/asm/inst.h, branch linux-4.9.y

mips: bpf: fix encoding bug for mm_srlv32_op

2019-02-12T18:44:54+00:00

[ Upstream commit 17f6c83fb5ebf7db4fcc94a5be4c22d5a7bfe428 ]

For micro-mips, srlv inside POOL32A encoding space should use 0x50
sub-opcode, NOT 0x90.

Some early version ISA doc describes the encoding as 0x90 for both srlv and
srav, this looks to me was a typo. I checked Binutils libopcode
implementation which is using 0x50 for srlv and 0x90 for srav.

v1->v2:
  - Keep mm_srlv32_op sorted by value.

Fixes: f31318fdf324 ("MIPS: uasm: Add srlv uasm instruction")
Cc: Markos Chandras 
Cc: Paul Burton 
Cc: linux-mips@vger.kernel.org
Acked-by: Jakub Kicinski 
Acked-by: Song Liu 
Signed-off-by: Jiong Wang 
Signed-off-by: Alexei Starovoitov 
Signed-off-by: Sasha Levin

MIPS: microMIPS: Fix decoding of swsp16 instruction

2018-11-10T15:42:44+00:00

[ Upstream commit cea8cd498f4f1c30ea27e3664b3c671e495c4fce ]

When the immediate encoded in the instruction is accessed, it is sign
extended due to being a signed value being assigned to a signed integer.
The ISA specifies that this operation is an unsigned operation.
The sign extension leads us to incorrectly decode:

801e9c8e:       cbf1            sw      ra,68(sp)

As having an immediate of 1073741809.

Since the instruction format does not specify signed/unsigned, and this
is currently the only location to use this instuction format, change it
to an unsigned immediate.

Fixes: bb9bc4689b9c ("MIPS: Calculate microMIPS ra properly when unwinding the stack")
Suggested-by: Paul Burton 
Signed-off-by: Matt Redfearn 
Reviewed-by: James Hogan 
Cc: Marcin Nowakowski 
Cc: Miodrag Dinic 
Cc: Ingo Molnar 
Cc: David Daney 
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/16957/
Signed-off-by: Ralf Baechle 
Signed-off-by: Sasha Levin

MIPS: inst.h: Rename cbcond{0,1}_op to pop{1,3}0_op

2016-07-05T14:09:07+00:00

The opcodes currently defined in inst.h as cbcond0_op & cbcond1_op are
actually defined in the MIPS base instruction set manuals as pop10 &
pop30 respectively. Rename them as such, for consistency with the
documentation.

Signed-off-by: Paul Burton 
Signed-off-by: James Hogan 
Acked-by: Ralf Baechle 
Cc: linux-mips@linux-mips.org
Signed-off-by: Paolo Bonzini

MIPS: inst.h: Rename b{eq,ne}zcji[al]c_op to pop{6,7}6_op

2016-07-05T14:08:59+00:00

The opcodes currently defined in inst.h as beqzcjic_op & bnezcjialc_op
are actually defined in the MIPS base instruction set manuals as pop66 &
pop76 respectively. Rename them as such, for consistency with the
documentation.

Signed-off-by: Paul Burton 
Signed-off-by: James Hogan 
Acked-by: Ralf Baechle 
Cc: linux-mips@linux-mips.org
Signed-off-by: Paolo Bonzini

MIPS: uasm: Add r6 MUL encoding

2016-07-05T14:08:40+00:00

Add the R6 MUL instruction encoding for 3 operand signed multiply to
uasm so that KVM can use uasm for generating its entry point code at
runtime on R6.

Signed-off-by: James Hogan 
Acked-by: Ralf Baechle 
Cc: linux-mips@linux-mips.org
Signed-off-by: Paolo Bonzini

MIPS: uasm: Add MTHI/MTLO instructions

2016-07-05T14:08:35+00:00

Add MTHI/MTLO instructions for writing to the hi & lo registers to uasm
so that KVM can use uasm for generating its entry point code at runtime.

Signed-off-by: James Hogan 
Acked-by: Ralf Baechle 
Cc: linux-mips@linux-mips.org
Signed-off-by: Paolo Bonzini

MIPS: uasm: Add DI instruction

2016-07-05T14:08:29+00:00

Add DI instruction for disabling interrupts to uasm so that KVM can use
uasm for generating its entry point code at runtime.

Signed-off-by: James Hogan 
Acked-by: Ralf Baechle 
Cc: linux-mips@linux-mips.org
Signed-off-by: Paolo Bonzini

MIPS: uasm: Add CFCMSA/CTCMSA instructions

2016-07-05T14:08:20+00:00

Add CFCMSA/CTCMSA instructions for accessing MSA control registers to
uasm so that KVM can use uasm for generating its entry point code at
runtime.

Signed-off-by: James Hogan 
Acked-by: Ralf Baechle 
Cc: linux-mips@linux-mips.org
Signed-off-by: Paolo Bonzini

MIPS: KVM: Convert emulation to use asm/inst.h

2016-06-15T21:58:17+00:00

Convert various MIPS KVM guest instruction emulation functions to decode
instructions (and encode translations) using the union mips_instruction
and related enumerations in asm/inst.h rather than #defines and
hardcoded values.

Signed-off-by: James Hogan 
Acked-by: Ralf Baechle 
Cc: Paolo Bonzini 
Cc: Radim Krčmář 
Cc: linux-mips@linux-mips.org
Cc: kvm@vger.kernel.org
Signed-off-by: Paolo Bonzini

MIPS: inst: Declare fsel_op for sel.fmt instruction

2016-05-13T12:02:21+00:00

Declare the opcode for the MIPSr6 sel.fmt instruction, as fsel_op in
order to match other FP op names.

Signed-off-by: Paul Burton 
Cc: Maciej W. Rozycki 
Cc: Leonid Yegoshin 
Cc: James Hogan 
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/13152/
Signed-off-by: Ralf Baechle