linux-stable.git/arch/mips/include/uapi/asm/inst.h, branch linux-4.8.y

MIPS: inst.h: Rename cbcond{0,1}_op to pop{1,3}0_op

2016-07-05T14:09:07+00:00

The opcodes currently defined in inst.h as cbcond0_op & cbcond1_op are
actually defined in the MIPS base instruction set manuals as pop10 &
pop30 respectively. Rename them as such, for consistency with the
documentation.

Signed-off-by: Paul Burton 
Signed-off-by: James Hogan 
Acked-by: Ralf Baechle 
Cc: linux-mips@linux-mips.org
Signed-off-by: Paolo Bonzini

MIPS: inst.h: Rename b{eq,ne}zcji[al]c_op to pop{6,7}6_op

2016-07-05T14:08:59+00:00

The opcodes currently defined in inst.h as beqzcjic_op & bnezcjialc_op
are actually defined in the MIPS base instruction set manuals as pop66 &
pop76 respectively. Rename them as such, for consistency with the
documentation.

Signed-off-by: Paul Burton 
Signed-off-by: James Hogan 
Acked-by: Ralf Baechle 
Cc: linux-mips@linux-mips.org
Signed-off-by: Paolo Bonzini

MIPS: uasm: Add r6 MUL encoding

2016-07-05T14:08:40+00:00

Add the R6 MUL instruction encoding for 3 operand signed multiply to
uasm so that KVM can use uasm for generating its entry point code at
runtime on R6.

Signed-off-by: James Hogan 
Acked-by: Ralf Baechle 
Cc: linux-mips@linux-mips.org
Signed-off-by: Paolo Bonzini

MIPS: uasm: Add MTHI/MTLO instructions

2016-07-05T14:08:35+00:00

Add MTHI/MTLO instructions for writing to the hi & lo registers to uasm
so that KVM can use uasm for generating its entry point code at runtime.

Signed-off-by: James Hogan 
Acked-by: Ralf Baechle 
Cc: linux-mips@linux-mips.org
Signed-off-by: Paolo Bonzini

MIPS: uasm: Add DI instruction

2016-07-05T14:08:29+00:00

Add DI instruction for disabling interrupts to uasm so that KVM can use
uasm for generating its entry point code at runtime.

Signed-off-by: James Hogan 
Acked-by: Ralf Baechle 
Cc: linux-mips@linux-mips.org
Signed-off-by: Paolo Bonzini

MIPS: uasm: Add CFCMSA/CTCMSA instructions

2016-07-05T14:08:20+00:00

Add CFCMSA/CTCMSA instructions for accessing MSA control registers to
uasm so that KVM can use uasm for generating its entry point code at
runtime.

Signed-off-by: James Hogan 
Acked-by: Ralf Baechle 
Cc: linux-mips@linux-mips.org
Signed-off-by: Paolo Bonzini

MIPS: KVM: Convert emulation to use asm/inst.h

2016-06-15T21:58:17+00:00

Convert various MIPS KVM guest instruction emulation functions to decode
instructions (and encode translations) using the union mips_instruction
and related enumerations in asm/inst.h rather than #defines and
hardcoded values.

Signed-off-by: James Hogan 
Acked-by: Ralf Baechle 
Cc: Paolo Bonzini 
Cc: Radim Krčmář 
Cc: linux-mips@linux-mips.org
Cc: kvm@vger.kernel.org
Signed-off-by: Paolo Bonzini

MIPS: inst: Declare fsel_op for sel.fmt instruction

2016-05-13T12:02:21+00:00

Declare the opcode for the MIPSr6 sel.fmt instruction, as fsel_op in
order to match other FP op names.

Signed-off-by: Paul Burton 
Cc: Maciej W. Rozycki 
Cc: Leonid Yegoshin 
Cc: James Hogan 
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/13152/
Signed-off-by: Ralf Baechle

MIPS: Loongson-3: Fast TLB refill handler

2016-05-13T12:02:15+00:00

Loongson-3A R2 has pwbase/pwfield/pwsize/pwctl registers in CP0 (this
is very similar to HTW) and lwdir/lwpte/lddir/ldpte instructions which
can be used for fast TLB refill.

[ralf@linux-mips.org: Resolve conflict.]

Signed-off-by: Huacai Chen 
Cc: Aurelien Jarno 
Cc: Steven J . Hill 
Cc: Fuxin Zhang 
Cc: Zhangjin Wu 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/12754/
Signed-off-by: Ralf Baechle

MIPS: Move KVM specific opcodes into asm/inst.h

2016-01-24T02:31:17+00:00

The header arch/mips/kvm/opcode.h defines a few extra opcodes which
aren't in arch/mips/include/uapi/asm/inst.h. There's nothing KVM
specific about them, so lets move them into inst.h where they belong and
delete the header.

Note that mfmcz_op is renamed to mfmc0_op to match the instruction set
manual, and wait_op was already added to inst.h in commit b0a3eae2b943
("MIPS: inst.h: define COP0 wait op"), merged in v3.16-rc1.

Signed-off-by: James Hogan 
Cc: Paolo Bonzini 
Cc: Gleb Natapov 
Cc: linux-mips@linux-mips.org
Cc: kvm@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/11895/
Signed-off-by: Ralf Baechle