linux-stable.git/arch/mips/include/uapi/asm/inst.h, branch linux-4.7.y

MIPS: inst: Declare fsel_op for sel.fmt instruction

2016-05-13T12:02:21+00:00

Declare the opcode for the MIPSr6 sel.fmt instruction, as fsel_op in
order to match other FP op names.

Signed-off-by: Paul Burton 
Cc: Maciej W. Rozycki 
Cc: Leonid Yegoshin 
Cc: James Hogan 
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/13152/
Signed-off-by: Ralf Baechle

MIPS: Loongson-3: Fast TLB refill handler

2016-05-13T12:02:15+00:00

Loongson-3A R2 has pwbase/pwfield/pwsize/pwctl registers in CP0 (this
is very similar to HTW) and lwdir/lwpte/lddir/ldpte instructions which
can be used for fast TLB refill.

[ralf@linux-mips.org: Resolve conflict.]

Signed-off-by: Huacai Chen 
Cc: Aurelien Jarno 
Cc: Steven J . Hill 
Cc: Fuxin Zhang 
Cc: Zhangjin Wu 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/12754/
Signed-off-by: Ralf Baechle

MIPS: Move KVM specific opcodes into asm/inst.h

2016-01-24T02:31:17+00:00

The header arch/mips/kvm/opcode.h defines a few extra opcodes which
aren't in arch/mips/include/uapi/asm/inst.h. There's nothing KVM
specific about them, so lets move them into inst.h where they belong and
delete the header.

Note that mfmcz_op is renamed to mfmc0_op to match the instruction set
manual, and wait_op was already added to inst.h in commit b0a3eae2b943
("MIPS: inst.h: define COP0 wait op"), merged in v3.16-rc1.

Signed-off-by: James Hogan 
Cc: Paolo Bonzini 
Cc: Gleb Natapov 
Cc: linux-mips@linux-mips.org
Cc: kvm@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/11895/
Signed-off-by: Ralf Baechle

MIPS: inst.h: Fix some instruction descriptions

2016-01-24T00:36:50+00:00

Fix the description of the microMIPS NOP16 encoding or MM_NOP16, which
is not equivalent to the MIPS16 NOP instruction.  This is 0x0c00 and
represents the microMIPS `MOVE16 $0, $0' operation, whereas MIPS16 NOP
is encoded as 0x6500, representing `MOVE $0, $16'.

Also fix a typo in `mm_fp0_format' description.

Signed-off-by: Maciej W. Rozycki 
Cc: Aurelien Jarno 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/12177/
Signed-off-by: Ralf Baechle

MIPS: math-emu: Correct the emulation of microMIPS ADDIUPC instruction

2016-01-24T00:36:10+00:00

Emulate the microMIPS ADDIUPC instruction directly in `mips_dsemul'.  If
executed in the emulation frame, this instruction produces an incorrect
result, because the value of the PC there is not the same as where the
instruction originated.

Reshape code so as to handle all microMIPS cases together.

Signed-off-by: Maciej W. Rozycki 
Cc: Aurelien Jarno 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/12175/
Signed-off-by: Ralf Baechle

MIPS: inst.h: Add new MIPS R6 FPU opcodes

2015-09-03T10:08:12+00:00

Add opcodes for the new MIPS R6 FPU instructions.

Signed-off-by: Markos Chandras 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10952/
Signed-off-by: Ralf Baechle

MIPS: Declare MSA MI10 instruction formats

2015-09-03T10:07:39+00:00

Declare a struct describing the MSA MI10 instruction format used for ld &
st instructions, for use by subsequent patches.

Signed-off-by: Paul Burton 
Cc: linux-mips@linux-mips.org
Cc: Leonid Yegoshin 
Cc: Steven J. Hill 
Cc: linux-kernel@vger.kernel.org
Cc: Markos Chandras 
Patchwork: https://patchwork.linux-mips.org/patch/10571/
Signed-off-by: Ralf Baechle

MIPS: Emulate the new MIPS R6 BNEZC and JIALC instructions

2015-02-17T15:37:35+00:00

MIPS R6 uses the

MIPS: Emulate the new MIPS R6 BEQZC and JIC instructions

2015-02-17T15:37:35+00:00

MIPS R6 uses the

MIPS: Emulate the new MIPS R6 BALC instruction

2015-02-17T15:37:35+00:00

MIPS R6 uses the