linux-stable.git/arch/mips/include/asm, branch v3.19.3

MIPS: HTW: Prevent accidental HTW start due to nested htw_{start, stop}

2015-03-06T22:57:37+00:00

commit ed4cbc81addbc076b016c5b979fd1a02f0897f0a upstream.

activate_mm() and switch_mm() call get_new_mmu_context() which in turn
can enable the HTW before the entryhi is changed with the new ASID.
Since the latter will enable the HTW in local_flush_tlb_all(),
then there is a small timing window where the HTW is running with the
new ASID but with an old pgd since the TLBMISS_HANDLER_SETUP_PGD
hasn't assigned a new one yet. In order to prevent that, we introduce a
simple htw counter to avoid starting HTW accidentally due to nested
htw_{start,stop}() sequences. Moreover, since various IPI calls can
enforce TLB flushing operations on a different core, such an operation
may interrupt another htw_{stop,start} in progress leading inconsistent
updates of the htw_seq variable. In order to avoid that, we disable the
interrupts whenever we update that variable.

Signed-off-by: Markos Chandras 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9118/
Signed-off-by: Ralf Baechle 
Signed-off-by: Greg Kroah-Hartman

MIPS: asm: pgtable: Prevent HTW race when updating PTEs

2015-03-06T22:57:28+00:00

commit fde3538a8a711aedf1173ecb2d45aed868f51c97 upstream.

Whenever we modify a page table entry, we need to ensure that the HTW
will not fetch a stable entry. And for that to happen we need to ensure
that HTW is stopped before we modify the said entry otherwise the HTW
may already be in the process of reading that entry and fetching the
old information. As a result of which, we replace the htw_reset() calls
with htw_{stop,start} in more appropriate places. This also removes the
remaining users of htw_reset() and as a result we drop that macro

Signed-off-by: Markos Chandras 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9116/
Signed-off-by: Ralf Baechle 
Signed-off-by: Greg Kroah-Hartman

MIPS: asm: pgtable: Add c0 hazards on HTW start/stop sequences

2015-03-06T22:57:28+00:00

commit 461d1597ffad7a826f8aaa63ab0727c37b632e34 upstream.

When we use htw_{start,stop}() outside of htw_reset(), we need
to ensure that c0 changes have been propagated properly before
we attempt to continue with subsequence memory operations.

Signed-off-by: Markos Chandras 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9114/
Signed-off-by: Ralf Baechle 
Signed-off-by: Greg Kroah-Hartman

MIPS: asm: asmmacro: Replace "add" instructions with "addu"

2015-03-06T22:57:28+00:00

commit 98a833c1fa4de0695830f77b2d13fd86693da298 upstream.

The "add" instruction is actually a macro in binutils and depending on
the size of the immediate it can expand to an "addi" instruction.
However, the "addi" instruction traps on overflows which is not
something we want on address calculation.

Link: http://www.linux-mips.org/archives/linux-mips/2015-01/msg00121.html
Cc: Paul Burton 
Cc: Maciej W. Rozycki 
Signed-off-by: Markos Chandras 
Signed-off-by: Greg Kroah-Hartman

MIPS: Fix syscall_get_nr for the syscall exit tracing.

2015-02-04T15:40:09+00:00

Register 2 is alredy overwritten by the return value when
syscall_trace_leave() is called.

Signed-off-by: Lars Persson 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9187/
Signed-off-by: Ralf Baechle

MIPS: mipsregs.h: Add write_32bit_cp1_register()

2015-01-30T22:04:59+00:00

Add a write_32bit_cp1_register() macro to compliment the
read_32bit_cp1_register() macro. This is to abstract whether .set
hardfloat needs to be used based on GAS_HAS_SET_HARDFLOAT.

The implementation of _read_32bit_cp1_register() .sets mips1 due to
failure of gas v2.19 to assemble cfc1 for Octeon (see commit
25c300030016 ("MIPS: Override assembler target architecture for
octeon.")). I haven't copied this over to _write_32bit_cp1_register() as
I'm uncertain whether it applies to ctc1 too, or whether anybody cares
about that version of binutils any longer.

Signed-off-by: James Hogan 
Cc: Ralf Baechle 
Cc: Paul Burton 
Cc: David Daney 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9172/
Signed-off-by: Ralf Baechle

MIPS: ARC: Fix build error.

2015-01-19T12:09:52+00:00

[...]
 struct component {
        ^
In file included from ./arch/mips/include/asm/sn/klconfig.h:58:0,
                 from ./arch/mips/include/asm/sn/module.h:12,
                 from ./arch/mips/include/asm/sn/node.h:8,
                 from ./arch/mips/include/asm/mach-ip35/mmzone.h:4,
                 from ./arch/mips/include/asm/mmzone.h:9,
                 from ./arch/mips/include/asm/mach-ip35/topology.h:7,
                 from ./arch/mips/include/asm/topology.h:11,
                 from include/linux/topology.h:35,
                 from include/linux/gfp.h:8,
                 from include/linux/device.h:29,
                 from drivers/base/component.c:14:
./arch/mips/include/asm/fw/arc/hinv.h:122:16: note: originally defined here
 typedef struct component {
                ^
make[2]: *** [drivers/base/component.o] Error 1
make[2]: Target `__build' not remade because of errors.
make[1]: *** [drivers/base] Error 2
make[1]: Target `__build' not remade because of errors.

Fix by using an nameless struct definition in the COMPONENT definition.
Which is what the ARC spec uses anyway.  While at it, do the same thing
for two other typedefs.

Signed-off-by: Ralf Baechle

MIPS: mips-cm: Fix sparse warnings

2015-01-13T14:53:09+00:00

Sparse emits a bunch of warnings in mips-cm.h due to casting away of
__iomem by the addr_gcr_*() functions:

arch/mips/include/asm/mips-cm.h:134:1: warning: cast removes address space of expression

And subsequent passing of the return values to __raw_readl() and
__raw_writel() in the read_gcr_*() and write_gcr_*() functions:

arch/mips/include/asm/mips-cm.h:134:1: warning: incorrect type in argument 2 (different address spaces)
arch/mips/include/asm/mips-cm.h:134:1:    expected void volatile [noderef] *mem
arch/mips/include/asm/mips-cm.h:134:1:    got unsigned int [usertype] *
arch/mips/include/asm/mips-cm.h:134:1: warning: incorrect type in argument 1 (different address spaces)
arch/mips/include/asm/mips-cm.h:134:1:    expected void const volatile [noderef] *mem
arch/mips/include/asm/mips-cm.h:134:1:    got unsigned int [usertype] *

Fix by adding __iomem to the addr_gcr_*() return type and cast.

Signed-off-by: James Hogan 
Cc: Paul Burton 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8874/
Signed-off-by: Ralf Baechle

MIPS: FRE: Use set/clear_c0_config5 instead of open coded sequences.

2015-01-13T14:53:08+00:00

Signed-off-by: Ralf Baechle

MIPS: Do not fiddle with FRE unless FRE is actually available.

2015-01-13T14:53:08+00:00

Commit 4227a2d4efc9c84f35826dc4d1e6dc183f6c1c05 (MIPS: Support for hybrid
FPRs) changes the kernel to execute read_c0_config5() even on processors
that don't have a Config5 register.  According to the arch spec the
behaviour of trying to read or write this register is UNDEFINED where this
register doesn't exist, that is merely looking at this register is
already cruel because that might kill a kitten.

In case of Qemu older than v2.2 Qemu has elected to implement this
UNDEFINED behaviour by taking a RI exception - which then fries the
kernel:

[...]
Freeing YAMON memory: 956k freed
Freeing unused kernel memory: 240K (80674000 - 806b0000)
Reserved instruction in kernel code[#1]:
CPU: 0 PID: 1 Comm: init Not tainted 3.18.0-rc6-00058-g4227a2d #26
task: 86047588 ti: 86048000 task.ti: 86048000
$ 0   : 00000000 77a638cc 00000000 00000000
[...]

For qemu v2.2.0 commit f31b035a9f10dc9b57f01c426110af845d453ce2
(target-mips: correctly handle access to unimplemented CP0 register)
changed the behaviour to returning zero on read and ignoring writes
which more matches how typical hardware implementations actually behave.

Signed-off-by: Ralf Baechle