linux-stable.git/arch/mips/include/asm/pgtable-bits.h, branch v3.18.76

MIPS: pgtable-bits: Define the CCA bit for WC writes on Ingenic cores

2014-09-22T11:35:52+00:00

Ingenic uses the CCA:1 bit to achieve write-combine memory writes.

Signed-off-by: Markos Chandras 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/7401/
Signed-off-by: Ralf Baechle

MIPS: pgtable-bits: Move the CCA bits out of the core's ifdef blocks

2014-09-22T11:35:52+00:00

Define all the CCA bits outside the ifdef blocks for specific cores
but also allow cores to override them if necessary.

Signed-off-by: Markos Chandras 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/7400/
Signed-off-by: Ralf Baechle

MIPS: Loongson: Add basic Loongson-3 definition

2014-03-31T16:17:12+00:00

Loongson-3 is a multi-core MIPS family CPU, it support MIPS64R2 fully.
Loongson-3 has the same IMP field (0x6300) as Loongson-2.

Loongson-3 has a hardware-maintained cache, system software doesn't
need to maintain coherency.

Loongson-3A is the first revision of Loongson-3, and it is the quad-
core version of Loongson-2G. Loongson-3A has a simplified version named
Loongson-2Gq, the main difference between Loongson-3A/2Gq is 3A has two
HyperTransport controller but 2Gq has only one. HT0 is used for cross-
chip interconnection and HT1 is used to link PCI bus. Therefore, 2Gq
cannot support NUMA but 3A can. For software, Loongson-2Gq is simply
identified as Loongson-3A.

Exsisting Loongson family CPUs:
Loongson-1: Loongson-1A, Loongson-1B, they are 32-bit MIPS CPUs.
Loongson-2: Loongson-2E, Loongson-2F, Loongson-2G, they are 64-bit
            single-core MIPS CPUs.
Loongson-3: Loongson-3A(including so-called Loongson-2Gq), they are
            64-bit multi-core MIPS CPUs.

Signed-off-by: Huacai Chen 
Signed-off-by: Hongliang Tao 
Signed-off-by: Hua Yan 
Tested-by: Alex Smith 
Reviewed-by: Alex Smith 
Cc: John Crispin 
Cc: Steven J. Hill 
Cc: Aurelien Jarno 
Cc: linux-mips@linux-mips.org
Cc: Fuxin Zhang 
Cc: Zhangjin Wu 
Patchwork: https://patchwork.linux-mips.org/patch/6629/
Signed-off-by: Ralf Baechle

MIPS: Whitespace cleanup.

2013-02-01T09:00:22+00:00

Having received another series of whitespace patches I decided to do this
once and for all rather than dealing with this kind of patches trickling
in forever.

Signed-off-by: Ralf Baechle

MIPS: Nuke trailing whitespace.

2013-02-01T09:00:21+00:00

Signed-off-by: Ralf Baechle

MIPS: PMC-Sierra Yosemite: Remove support.

2012-12-13T17:15:30+00:00

Nobody seems to be interested anymore and upstream also never had an
ethernet driver.

Signed-off-by: Ralf Baechle

MIPS: Transparent Huge Pages support

2012-12-12T15:48:52+00:00

Signed-off-by: Ralf Baechle

MIPS: Control huge tlb support via Kconfig symbol MIPS_HUGE_TLB_SUPPORT

2012-12-12T15:48:47+00:00

We need Huge TLBs for HUGETLB_PAGE, or the soon to follow
TRANSPARENT_HUGEPAGE.  collect this information under a single Kconfig
symbol.

Signed-off-by: David Daney

MIPS: tlbex: Better debug output.

2012-11-26T12:41:06+00:00

Pgtable bits are assigned dynamically depending on processor feature and
statically based on kernel configuration.  To make sense out of the
disassembled TLB exception handlers a list of the actual assignments
used for a particular configuration and hardware setup can be very useful.

Output the actual TLB exception handlers in a format that simplifies their
post processsing from dmesg output.

Signed-off-by: Ralf Baechle

MIPS: Replace 'kernel_uses_smartmips_rixi' with 'cpu_has_rixi'.

2012-09-13T22:00:34+00:00

Remove usage of the 'kernel_uses_smartmips_rixi' macro from all files
and use new 'cpu_has_rixi' instead.

Signed-off-by: Steven J. Hill 
Acked-by: David Daney