linux-stable.git/arch/mips/include/asm/cpu-features.h, branch linux-5.0.y

MIPS: Hardcode cpu_has_mips* where target ISA allows

2018-11-27T06:49:20+00:00

In the same vein as commit 93e01942a6eb ("MIPS: Hardcode cpu_has_* where
known at compile time due to ISA"), we can use our knowledge of the ISA
being targeted by the kernel build to make cpu_has_mips* macros
compile-time constant in some cases. This allows the compiler greater
opportunity to optimize out code which will never execute.

Signed-off-by: Paul Burton 
Patchwork: https://patchwork.linux-mips.org/patch/21245/
Cc: linux-mips@linux-mips.org

MIPS: Use Kconfig to select CPU_NO_EFFICIENT_FFS

2018-11-12T22:26:16+00:00

Select CONFIG_CPU_NO_EFFICIENT_FFS via Kconfig when the kernel is
configured for a pre-MIPS32r1 CPU, rather than defining its equivalent
in asm/cpu-features.h based upon overrides of cpu_has_mips* macros.

The latter only works if a platform has an cpu-feature-overrides.h
header which defines cpu_has_mips* macros, which are not generally
needed. There are many cases where we know that the target ISA for a
kernel build is MIPS32r1 or later & thus includes the CLZ instruction,
without requiring any overrides from the platform. Using Kconfig allows
us to take those into account, and more naturally make a decision about
instruction support using information about the target ISA.

Signed-off-by: Paul Burton 
Patchwork: https://patchwork.linux-mips.org/patch/21045/
Cc: Andrew Morton 
Cc: Zhaoxiu Zeng 
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org

MIPS: Hardcode cpu_has_fpu=0 when CONFIG_MIPS_FP_SUPPORT=n

2018-11-09T18:23:15+00:00

When CONFIG_MIPS_FP_SUPPORT=n we don't support floating point, so
there's no point in detecting presence of an FPU. Hardcode
cpu_has_fpu=0 such that we optimize out code that makes use of the FPU.

Signed-off-by: Paul Burton 
Patchwork: https://patchwork.linux-mips.org/patch/21005/
Cc: linux-mips@linux-mips.org

MIPS: Hardcode cpu_has_mmips=1 for microMIPS kernels

2018-11-08T18:23:38+00:00

If we built the kernel targeting the microMIPS ISA then the very fact
that the kernel is running implies that the CPU supports microMIPS. Thus
we can hardcode cpu_has_mmips to 1 allowing the compiler greater scope
for optimisation due to the compile-time constant.

Signed-off-by: Paul Burton 
Patchwork: https://patchwork.linux-mips.org/patch/21022/
Cc: linux-mips@linux-mips.org

MIPS: Hardcode cpu_has_* where known at compile time due to ISA

2018-07-24T21:09:13+00:00

Many architectural features have over time moved from being optional to
either be required or removed by newer architecture releases. This means
that in many cases we can know at compile time whether a feature will be
supported or not purely due to the knowledge we have about the ISA the
kernel build is targeting.

This patch introduces a bunch of utility macros for checking for
supported options, ASEs & combinations of those with ISA revisions. It
then makes use of these in the default definitions of cpu_has_* macros.
The result is that many of the macros become compile-time constant,
allowing more optimisation opportunities for the compiler - particularly
with kernels built for later ISA revisions.

To demonstrate the effect of this patch, the following table shows the
size in bytes of the kernel binary as reported by scripts/bloat-o-meter
for v4.12-rc4 maltasmvp_defconfig kernels with & without this patch. A
variant of maltasmvp_defconfig with CONFIG_CPU_MIPS32_R6 selected is
also shown, to demonstrate that MIPSr6 systems benefit more due to extra
features becoming required by that architecture revision. Builds of
pistachio_defconfig are also shown, as although this is a MIPSr2
platform it doesn't hardcode any features in a machine-specific
cpu-feature-overrides.h, which allows it to gain more from this patch
than the equivalent Malta r2 build.

     Config         | Before  | After   |  Change
    ----------------|---------|---------|---------
     maltasmvp      | 7248316 | 7247714 |    -602
     maltasmvp + r6 | 6955595 | 6950777 |   -4818
     pistachio      | 8650977 | 8363898 | -287079

Signed-off-by: Paul Burton 
Patchwork: https://patchwork.linux-mips.org/patch/16360/
Cc: Joshua Kinard 
Cc: Ralf Baechle 
Cc: linux-mips@linux-mips.org

MIPS: perf: More robustly probe for the presence of per-tc counters

2018-05-15T14:16:16+00:00

The presence of per TC performance counters is now detected by
cpu-probe.c and indicated by MIPS_CPU_MT_PER_TC_PERF_COUNTERS in
cpu_data. Switch detection of the feature to use this new flag rather
than blindly testing the implementation specific config7 register with a
magic number.

Signed-off-by: Matt Redfearn 
Cc: Ralf Baechle 
Cc: Florian Fainelli 
Cc: Maciej W. Rozycki 
Cc: Paul Burton 
Cc: Peter Zijlstra 
Cc: Ingo Molnar 
Cc: Arnaldo Carvalho de Melo 
Cc: Alexander Shishkin 
Cc: Jiri Olsa 
Cc: Namhyung Kim 
Cc: Robert Richter 
Cc: linux-mips@linux-mips.org
Cc: oprofile-list@lists.sf.net
Patchwork: https://patchwork.linux-mips.org/patch/19142/
Signed-off-by: James Hogan

MIPS: cpu-features.h: Replace __mips_isa_rev with MIPS_ISA_REV

2018-03-09T11:22:46+00:00

Remove the need to check that __mips_isa_rev is defined by using the
newly added MIPS_ISA_REV.

Signed-off-by: Matt Redfearn 
Cc: Ralf Baechle 
Cc: Paul Burton 
Cc: "Maciej W. Rozycki" 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/18675/
Signed-off-by: James Hogan

MIPS: Introduce cpu_tcache_line_size

2017-08-07T22:02:27+00:00

There exist macros to return the cache line size of the L1 dcache and L2
scache but there is currently no macro for the L3 tcache. Add this macro
which will be used by the following patch "MIPS: PCI: Fix
smp_processor_id() in preemptible"

Signed-off-by: Matt Redfearn 
Cc: Maciej W. Rozycki 
Cc: James Hogan 
Cc: Paul Burton 
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/16871/
Signed-off-by: Ralf Baechle

MIPS: MIPS16e2: Identify ASE presence

2017-07-05T12:06:44+00:00

Identify the presence of the MIPS16e2 ASE as per the architecture
specification[1], by checking for CP0 Config5.CA2 bit being 1[2].

References:

[1] "MIPS32 Architecture for Programmers: MIPS16e2 Application-Specific
    Extension Technical Reference Manual", Imagination Technologies
    Ltd., Document Number: MD01172, Revision 01.00, April 26, 2016,
    Section 1.2 "Software Detection of the ASE", p. 5

[2] "MIPS32 interAptiv Multiprocessing System Software User's Manual",
    Imagination Technologies Ltd., Document Number: MD00904, Revision
    02.01, June 15, 2016, Section 2.2.1.6 "Device Configuration 5 --
    Config5 (CP0 Register 16, Select 5)", pp. 71-72

Signed-off-by: Maciej W. Rozycki 
Reviewed-by: James Hogan 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/16094/
Signed-off-by: Ralf Baechle

MIPS: Add CPU shared FTLB feature detection

2017-06-29T00:42:29+00:00

Some systems share FTLB RAMs or entries between sibling CPUs (ie.
hardware threads, or VP(E)s, within a core). These properties require
kernel handling in various places. As a start this patch introduces
cpu_has_shared_ftlb_ram & cpu_has_shared_ftlb_entries feature macros
which we set appropriately for I6400 & I6500 CPUs. Further patches will
make use of these macros as appropriate.

Signed-off-by: Paul Burton 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/16202/
Signed-off-by: Ralf Baechle