linux-stable.git/arch/mips/include/asm/atomic.h, branch linux-4.3.y

atomic: Provide atomic_{or,xor,and}

2015-07-27T12:06:24+00:00

Implement atomic logic ops -- atomic_{or,xor,and}.

These will replace the atomic_{set,clear}_mask functions that are
available on some archs.

Signed-off-by: Peter Zijlstra (Intel) 
Signed-off-by: Thomas Gleixner

mips: Provide atomic_{or,xor,and}

2015-07-27T12:06:22+00:00

Implement atomic logic ops -- atomic_{or,xor,and}.

These will replace the atomic_{set,clear}_mask functions that are
available on some archs.

Acked-by: Ralf Baechle 
Signed-off-by: Peter Zijlstra (Intel) 
Signed-off-by: Thomas Gleixner

MIPS: asm: atomic: Update ISA constraints for MIPS R6 support

2015-02-17T15:37:22+00:00

MIPS R6 changed the opcodes for LL/SC instructions so we need to
set the correct ISA level.

Cc: Matthew Fortune 
Signed-off-by: Markos Chandras

MIPS: asm: Rename GCC_OFF12_ASM to GCC_OFF_SMALL_ASM

2015-02-17T15:37:21+00:00

The GCC_OFF12_ASM macro is used for 12-bit immediate constrains
but we will also use it for 9-bit constrains on MIPS R6 so we
rename it to something more appropriate.

Cc: Maciej W. Rozycki 
Signed-off-by: Markos Chandras

MIPS: atomic.h: Reformat to fit in 79 columns

2014-11-24T06:45:37+00:00

Signed-off-by: Maciej W. Rozycki 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8484/
Signed-off-by: Ralf Baechle

MIPS: Fix microMIPS LL/SC immediate offsets

2014-11-24T06:45:36+00:00

In the microMIPS encoding some memory access instructions have their
immediate offset reduced to 12 bits only.  That does not match the GCC
`R' constraint we use in some places to satisfy the requirement,
resulting in build failures like this:

{standard input}: Assembler messages:
{standard input}:720: Error: macro used $at after ".set noat"
{standard input}:720: Warning: macro instruction expanded into multiple instructions

Fix the problem by defining a macro, `GCC_OFF12_ASM', that expands to
the right constraint depending on whether microMIPS or standard MIPS
code is produced.  Also apply the fix to where `m' is used as in the
worst case this change does nothing, e.g. where the pointer was already
in a register such as a function argument and no further offset was
requested, and in the best case it avoids an extraneous sequence of up
to two instructions to load the high 20 bits of the address in the LL/SC
loop.  This reduces the risk of lock contention that is the higher the
more instructions there are in the critical section between LL and SC.

Strictly speaking we could just bulk-replace `R' with `ZC' as the latter
constraint adjusts automatically depending on the ISA selected.
However it was only introduced with GCC 4.9 and we keep supporing older
compilers for the standard MIPS configuration, hence the slightly more
complicated approach I chose.

The choice of a zero-argument function-like rather than an object-like
macro was made so that it does not look like a function call taking the
C expression used for the constraint as an argument.  This is so as not
to confuse the reader or formatting checkers like `checkpatch.pl' and
follows previous practice.

Signed-off-by: Maciej W. Rozycki 
Signed-off-by: Steven J. Hill 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8482/
Signed-off-by: Ralf Baechle

locking,arch: Use ACCESS_ONCE() instead of cast to volatile in atomic_read()

2014-10-03T04:06:23+00:00

Use the much more reader friendly ACCESS_ONCE() instead of the cast to volatile.
This is purely a stylistic change.

Signed-off-by: Pranith Kumar 
Acked-by: Jesper Nilsson 
Acked-by: Hans-Christian Egtvedt 
Acked-by: Max Filippov 
Signed-off-by: Peter Zijlstra (Intel) 
Cc: Linus Torvalds 
Cc: linux-arch@vger.kernel.org
Link: http://lkml.kernel.org/r/1411482607-20948-1-git-send-email-bobby.prani@gmail.com
Signed-off-by: Ingo Molnar

locking, mips: Fix atomics

2014-09-10T09:45:06+00:00

The patch folding the atomic ops had two silly fails in the _return
primitives.

Fixes: ef31563e950c ("locking,arch,mips: Fold atomic_ops")
Reported-by: Guenter Roeck 
Tested-by: Guenter Roeck 
Signed-off-by: Peter Zijlstra (Intel) 
Cc: Bart Van Assche 
Cc: Hannes Reinecke 
Cc: Linus Torvalds 
Cc: Maciej W. Rozycki 
Cc: Markos Chandras 
Cc: Paul Burton 
Cc: Paul E. McKenney 
Cc: Ralf Baechle 
Cc: Stephen Rothwell 
Link: http://lkml.kernel.org/r/20140902202126.GA3190@worktop.ger.corp.intel.com
Signed-off-by: Ingo Molnar

locking,arch,mips: Fold atomic_ops

2014-08-14T10:48:09+00:00

Many of the atomic op implementations are the same except for one
instruction; fold the lot into a few CPP macros and reduce LoC.

This also prepares for easy addition of new ops.

Signed-off-by: Peter Zijlstra 
Cc: Linus Torvalds 
Cc: Maciej W. Rozycki 
Cc: Paul E. McKenney 
Cc: Ralf Baechle 
Cc: linux-mips@linux-mips.org
Link: http://lkml.kernel.org/r/20140508135852.521548500@infradead.org
Signed-off-by: Ingo Molnar

arch,mips: Convert smp_mb__*()

2014-04-18T12:20:38+00:00

MIPS is interesting and has hardware variants that reorder over ll/sc
as well as those that do not.

Implement the 2 new barrier functions as per the old barriers.

Signed-off-by: Peter Zijlstra 
Acked-by: Paul E. McKenney 
Link: http://lkml.kernel.org/n/tip-9ph49jbae3hol9v721sbc2g6@git.kernel.org
Cc: Linus Torvalds 
Cc: Maciej W. Rozycki" 
Cc: Ralf Baechle 
Cc: Will Deacon 
Cc: linux-kernel@vger.kernel.org
Cc: linux-mips@linux-mips.org
Signed-off-by: Ingo Molnar