linux-stable.git/arch/mips/boot, branch v5.15

MIPS: mscc: ocelot: mark the phy-mode for internal PHY ports

2021-08-21T08:38:48+00:00

The ocelot driver was converted to phylink, and that expects a valid
phy_interface_t. Without a phy-mode, of_get_phy_mode returns
PHY_INTERFACE_MODE_NA, which is not ideal because phylink rejects that.

The ocelot driver was patched to treat PHY_INTERFACE_MODE_NA as
PHY_INTERFACE_MODE_INTERNAL to work with the broken DT blobs, but we
should fix the device trees and specify the phy-mode too.

Signed-off-by: Vladimir Oltean 
Signed-off-by: Thomas Bogendoerfer

MIPS: mscc: ocelot: disable all switch ports by default

2021-08-21T08:38:29+00:00

The ocelot switch driver used to ignore ports which do not have a
phy-handle property and not probe those, but this is not quite ok since
it is valid to not have a phy-handle property if there is a fixed-link.

It seems that checking for a phy-handle was a proxy for the proper check
which is for the status, but that doesn't make a lot of sense, since the
ocelot driver already iterates using for_each_available_child_of_node
which skips the disabled ports, so I have no idea.

Anyway, a widespread pattern in device trees is for a SoC dtsi to
disable by default all hardware, and let board dts files enable what is
used. So let's do that and enable only the ports with a phy-handle in
the pcb120 and pcb123 device tree files.

Signed-off-by: Vladimir Oltean 
Signed-off-by: Thomas Bogendoerfer

MIPS: Retire MACH_PISTACHIO

2021-08-12T14:01:50+00:00

Now it can be replaced by generic kernel.

Signed-off-by: Jiaxun Yang 
Signed-off-by: Thomas Bogendoerfer

MIPS: DTS: Pistachio add missing cpc and cdmm

2021-08-12T14:01:49+00:00

CPC and CDMM addresses are adjustable and we should tell kernel
how to place them in devicetree.

Note that MACH_PISTACHIO code hardcoded CDMM base to 0x1bdd0000,
however it will collide with GIC address range. As we don't have
any CDMM device on this platform it won't be a problem.
I found another spare range, 0x1bdf0000~0x1be00000 to place CDMM
instead.

Signed-off-by: Jiaxun Yang 
Signed-off-by: Thomas Bogendoerfer

MIPS: generic: Allow generating FIT image for Marduk board

2021-08-12T14:01:49+00:00

Marduk is based on IMG pistachio SoC. The platform is using
MIPS UHI booting protocol and does have a proper devicetree
implement, thus it could be a part of generic kernel.

Signed-off-by: Jiaxun Yang 
Signed-off-by: Thomas Bogendoerfer

Merge tag 'mips_5.14_1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux

2021-07-10T17:36:33+00:00

Pull MIPS fixes from Thomas Bogendoerfer:

 - fix for accesing gic via vdso

 - two build fixes

* tag 'mips_5.14_1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux:
  MIPS: vdso: Invalid GIC access through VDSO
  mips: disable branch profiling in boot/decompress.o
  mips: always link byteswap helpers into decompressor

mips: disable branch profiling in boot/decompress.o

2021-07-05T15:04:01+00:00

Use DISABLE_BRANCH_PROFILING for arch/mips/boot/compressed/decompress.o
to prevent linkage errors.

mips64-linux-ld: arch/mips/boot/compressed/decompress.o: in function `LZ4_decompress_fast_extDict':
decompress.c:(.text+0x8c): undefined reference to `ftrace_likely_update'
mips64-linux-ld: decompress.c:(.text+0xf4): undefined reference to `ftrace_likely_update'
mips64-linux-ld: decompress.c:(.text+0x200): undefined reference to `ftrace_likely_update'
mips64-linux-ld: decompress.c:(.text+0x230): undefined reference to `ftrace_likely_update'
mips64-linux-ld: decompress.c:(.text+0x320): undefined reference to `ftrace_likely_update'
mips64-linux-ld: arch/mips/boot/compressed/decompress.o:decompress.c:(.text+0x3f4): more undefined references to `ftrace_likely_update' follow

Fixes: e76e1fdfa8f8 ("lib: add support for LZ4-compressed kernel")
Reported-by: kernel test robot 
Signed-off-by: Randy Dunlap 
Cc: Thomas Bogendoerfer 
Cc: linux-mips@vger.kernel.org
Cc: Kyungsik Lee 
Signed-off-by: Thomas Bogendoerfer

mips: always link byteswap helpers into decompressor

2021-07-05T15:03:11+00:00

My series to clean up the unaligned access implementation
across architectures caused some mips randconfig builds to
fail with:

   mips64-linux-ld: arch/mips/boot/compressed/decompress.o: in function `decompress_kernel':
   decompress.c:(.text.decompress_kernel+0x54): undefined reference to `__bswapsi2'

It turns out that this problem has already been fixed for the XZ
decompressor but now it also shows up in (at least) LZO and LZ4.  From my
analysis I concluded that the compiler could always have emitted those
calls, but the different implementation allowed it to make otherwise
better decisions about not inlining the byteswap, which results in the
link error when the out-of-line code is missing.

While it could be addressed by adding it to the two decompressor
implementations that are known to be affected, but as this only adds
112 bytes to the kernel, the safer choice is to always add them.

Fixes: c50ec6787536 ("MIPS: zboot: Fix the build with XZ compression on older GCC versions")
Fixes: 0652035a5794 ("asm-generic: unaligned: remove byteshift helpers")
Link: https://lore.kernel.org/linux-mm/202106301304.gz2wVY9w-lkp@intel.com/
Link: https://lore.kernel.org/linux-mm/202106260659.TyMe8mjr-lkp@intel.com/
Link: https://lore.kernel.org/linux-mm/202106172016.onWT6Tza-lkp@intel.com/
Link: https://lore.kernel.org/linux-mm/202105231743.JJcALnhS-lkp@intel.com/
Signed-off-by: Arnd Bergmann 
Signed-off-by: Thomas Bogendoerfer

Merge tag 'mips_5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux

2021-07-02T00:03:11+00:00

Pull MIPS updates from Thomas Bogendoerfer:

 - add support for OpeneEmbed SOM9331 board

 - Ingenic fixes/improvments

 - other fixes and cleanups

* tag 'mips_5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (39 commits)
  MIPS: Fix PKMAP with 32-bit MIPS huge page support
  MIPS: CI20: Add second percpu timer for SMP.
  MIPS: CI20: Reduce clocksource to 750 kHz.
  MIPS: Ingenic: Add MAC syscon nodes for Ingenic SoCs.
  dt-bindings: clock: Add documentation for MAC PHY control bindings.
  MIPS: X1830: Respect cell count of common properties.
  MIPS: set mips32r5 for virt extensions
  MIPS: loongsoon64: Reserve memory below starting pfn to prevent Oops
  MIPS: MT extensions are not available on MIPS32r1
  mips/kvm: Use BUG_ON instead of if condition followed by BUG
  MIPS: OCTEON: octeon-usb: Use devm_platform_get_and_ioremap_resource()
  MIPS: add PMD table accounting into MIPS'pmd_alloc_one
  MIPS: Loongson64: fix spelling of SPDX tag
  MIPS: ingenic: rs90: Add dedicated VRAM memory region
  MIPS: ingenic: gcw0: Set codec to cap-less mode for FM radio
  MIPS: ingenic: jz4780: Fix I2C nodes to match DT doc
  MIPS: ingenic: Select CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
  MIPS: Kconfig: ingenic: Ensure MACH_INGENIC_GENERIC selects all SoCs
  MIPS: cpu-probe: Fix FPU detection on Ingenic JZ4760(B)
  MIPS: boot: Support specifying UART port on Ingenic SoCs
  ...

MIPS: CI20: Add second percpu timer for SMP.

2021-06-30T12:37:16+00:00

1.Add a new TCU channel as the percpu timer of core1, this is to
  prepare for the subsequent SMP support. The newly added channel
  will not adversely affect the current single-core state.
2.Adjust the position of TCU node to make it consistent with the
  order in jz4780.dtsi file.

Tested-by: Nikolaus Schaller  # on CI20
Signed-off-by: 周琰杰 (Zhou Yanjie) 
Acked-by: Paul Cercueil 
Signed-off-by: Thomas Bogendoerfer