linux-stable.git/arch/c6x, branch v3.3

C6X: remove dead code from entry.S

2012-03-16T13:27:57+00:00

The ENDPROC() on sys_fadvise64_c6x() in arch/c6x/kernel/entry.S is
outside of the conditional block with the matching ENTRY() macro. This
leads a newer (v2.22 vs. v2.20) assembler to complain:

  /tmp/ccGZBaPT.s: Assembler messages:
  /tmp/ccGZBaPT.s: Error: .size expression for sys_fadvise64_c6x does not evaluate to a constant

The conditional block became dead code when c6x switched to generic
unistd.h and should be removed along with the offending ENDPROC().

Signed-off-by: Mark Salter 
Acked-by: David Howells

C6X: fix KSTK_EIP and KSTK_ESP macros

2012-03-07T16:28:22+00:00

There was a latent typo in the C6X KSTK_EIP and KSTK_ESP macros which
caused a problem with a new patch which used them. The broken definitions
were of the form:

  #define KSTK_FOO(tsk) (task_pt_regs(task)->foo)

Note the use of task vs tsk. This actually worked before because the
only place in the kernel which used these macros passed in a local
pointer named task.

Signed-off-by: Mark Salter

Kbuild: Use dtc's -d (dependency) option

2012-02-15T02:14:44+00:00

This hooks dtc into Kbuild's dependency system.

Thus, for example, "make dtbs" will rebuild tegra-harmony.dtb if only
tegra20.dtsi has changed yet tegra-harmony.dts has not. The previous
lack of this feature recently caused me to have very confusing "git
bisect" results.

For ARM, it's obvious what to add to $(targets). I'm not familiar enough
with other architectures to know what to add there. Powerpc appears to
already add various .dtb files into $(targets), but the other archs may
need something added to $(targets) to work.

Signed-off-by: Stephen Warren 
Acked-by: Shawn Guo 
Acked-by: Mark Salter

C6X: replace tick_nohz_stop/restart_sched_tick calls

2012-01-08T20:13:16+00:00

The following commits replaced the tick_nohz_{stop,restart}_sched_tick
API with separate tick and rcu calls:

  280f06774afedf849f0b34248ed6aff57d0f6908
  2bbb6817c0ac1b5f2a68d720f364f98eeb1ac4fd
  1268fbc746ea1cd279886a740dcbad4ba5232225

This patch replaces the C6X use of the old API with the newer interfaces.

Signed-off-by: Mark Salter

C6X: add register_cpu call

2012-01-08T20:13:10+00:00

Commit ccbc60d3e19a1b6ae66ca0d89b3da02dde62088b requires CPU
topology information even in !SMP cases. This requires C6X to
add a call tp register_cpu() in order to avoid a panic at
boot time.

Signed-off-by: Mark Salter

C6X: deal with memblock API changes

2012-01-08T20:12:44+00:00

Recent memblock related commits require the following C6X changes:

  * commit 24aa07882b672fff2da2f5c955759f0bd13d32d5
    asm/memblock.h no longer required

  * commit 1440c4e2c918532f39131c3330fe2226e16be7b6
    memblock_analyze() no longer needed to update total size

  * commit fe091c208a40299fba40e62292a610fb91e44b4e
    memblock_init() no longer needed

Signed-off-by: Mark Salter

C6X: fix timer64 initialization

2012-01-08T20:12:17+00:00

Some SoCs have a timer block enable controlled through the DSCR registers.
There is a problem in the timer64 driver initialization where the code
accesses a timer register to get the divisor used to calculate timer clock
rate. If the timer block has not been enabled when this register read takes
place, an exception is generated. This patch makes sure that the timer block
is enabled before accessing the registers.

Signed-off-by: Mark Salter

C6X: fix layout of EMIFA registers

2012-01-08T20:12:09+00:00

Signed-off-by: Mark Salter

C6X: DSCR - Device State Configuration Registers

2011-10-06T23:48:36+00:00

All SoCs provide an area of device configuration registers called the DSCR. The
location of specific registers as well as their use varies considerably from
implementation to implementation. Rather than having to rely on additional
SoC-specific DSCR code for each new supported SoC, this code generalize things
as much as possible using device tree properties. Initialization must take
place early on (setup_arch time) in case the event timer device needs to be
enable via the DSCR.

Signed-off-by: Mark Salter 
Signed-off-by: Aurelien Jacquiot 
Acked-by: Arnd Bergmann

C6X: EMIF - External Memory Interface

2011-10-06T23:48:29+00:00

Several SoC parts provide a simple bridge to support external memory mapped
devices. This code probes the device tree for an EMIF node and sets up the
bridge registers if such a node is found. Beyond initial set up, there is no
further need to access the bridge control registers. External devices on the
bus are accessed through their MMIO registers using suitable drivers. The
bridge hardware does provide for timeout and other error interrupts, but these
are not yet supported.

Signed-off-by: Mark Salter 
Signed-off-by: Aurelien Jacquiot 
Acked-by: Arnd Bergmann