linux-stable.git/arch/c6x/include, branch v3.3

C6X: fix KSTK_EIP and KSTK_ESP macros

2012-03-07T16:28:22+00:00

There was a latent typo in the C6X KSTK_EIP and KSTK_ESP macros which
caused a problem with a new patch which used them. The broken definitions
were of the form:

  #define KSTK_FOO(tsk) (task_pt_regs(task)->foo)

Note the use of task vs tsk. This actually worked before because the
only place in the kernel which used these macros passed in a local
pointer named task.

Signed-off-by: Mark Salter

C6X: deal with memblock API changes

2012-01-08T20:12:44+00:00

Recent memblock related commits require the following C6X changes:

  * commit 24aa07882b672fff2da2f5c955759f0bd13d32d5
    asm/memblock.h no longer required

  * commit 1440c4e2c918532f39131c3330fe2226e16be7b6
    memblock_analyze() no longer needed to update total size

  * commit fe091c208a40299fba40e62292a610fb91e44b4e
    memblock_init() no longer needed

Signed-off-by: Mark Salter

C6X: DSCR - Device State Configuration Registers

2011-10-06T23:48:36+00:00

All SoCs provide an area of device configuration registers called the DSCR. The
location of specific registers as well as their use varies considerably from
implementation to implementation. Rather than having to rely on additional
SoC-specific DSCR code for each new supported SoC, this code generalize things
as much as possible using device tree properties. Initialization must take
place early on (setup_arch time) in case the event timer device needs to be
enable via the DSCR.

Signed-off-by: Mark Salter 
Signed-off-by: Aurelien Jacquiot 
Acked-by: Arnd Bergmann

C6X: general SoC support

2011-10-06T23:48:26+00:00

This patch provides a soc_ops struct which provides hooks for SoC functionality
which doesn't fit well into other places.

Signed-off-by: Mark Salter 
Signed-off-by: Aurelien Jacquiot 
Acked-by: Arnd Bergmann

C6X: library code

2011-10-06T23:48:23+00:00

Original port to early 2.6 kernel using TI COFF toolchain.
Brought up to date by Mark Salter 

Signed-off-by: Aurelien Jacquiot 
Signed-off-by: Mark Salter 
Acked-by: Arnd Bergmann

C6X: headers

2011-10-06T23:48:20+00:00

Original port to early 2.6 kernel using TI COFF toolchain.
Brought up to date by Mark Salter 

Signed-off-by: Aurelien Jacquiot 
Signed-off-by: Mark Salter 
Acked-by: Arnd Bergmann

C6X: ptrace support

2011-10-06T23:48:17+00:00

Original port to early 2.6 kernel using TI COFF toolchain.
Brought up to date by Mark Salter 

Signed-off-by: Aurelien Jacquiot 
Signed-off-by: Mark Salter 
Acked-by: Arnd Bergmann

C6X: loadable module support

2011-10-06T23:48:13+00:00

Original port to early 2.6 kernel using TI COFF toolchain.
Brought up to date by Mark Salter 

Signed-off-by: Aurelien Jacquiot 
Signed-off-by: Mark Salter 
Acked-by: Arnd Bergmann

C6X: cache control

2011-10-06T23:48:10+00:00

Original port to early 2.6 kernel using TI COFF toolchain.
Brought up to date by Mark Salter 

Signed-off-by: Aurelien Jacquiot 
Signed-off-by: Mark Salter 
Acked-by: Arnd Bergmann

C6X: clocks

2011-10-06T23:48:07+00:00

The C6X SoCs contain several PLL controllers each with up to 16 clock outputs
feeding into the cores or peripheral clock domains. The hardware is very similar
to arm/mach-davinci clocks. This is still a work in progress which needs to be
updated once device tree clock binding changes shake out.

Signed-off-by: Mark Salter 
Signed-off-by: Aurelien Jacquiot 
Acked-by: Arnd Bergmann