linux-stable.git/arch/arm, branch v5.9.2

ARM: dts: meson8: remove two invalid interrupt lines from the GPU node

2020-10-29T09:12:06+00:00

[ Upstream commit 737e7610b545cc901a9696083c1824a7104b8d1b ]

The 3.10 vendor kernel defines the following GPU 20 interrupt lines:
  #define INT_MALI_GP                 AM_IRQ(160)
  #define INT_MALI_GP_MMU             AM_IRQ(161)
  #define INT_MALI_PP                 AM_IRQ(162)
  #define INT_MALI_PMU                AM_IRQ(163)
  #define INT_MALI_PP0                AM_IRQ(164)
  #define INT_MALI_PP0_MMU            AM_IRQ(165)
  #define INT_MALI_PP1                AM_IRQ(166)
  #define INT_MALI_PP1_MMU            AM_IRQ(167)
  #define INT_MALI_PP2                AM_IRQ(168)
  #define INT_MALI_PP2_MMU            AM_IRQ(169)
  #define INT_MALI_PP3                AM_IRQ(170)
  #define INT_MALI_PP3_MMU            AM_IRQ(171)
  #define INT_MALI_PP4                AM_IRQ(172)
  #define INT_MALI_PP4_MMU            AM_IRQ(173)
  #define INT_MALI_PP5                AM_IRQ(174)
  #define INT_MALI_PP5_MMU            AM_IRQ(175)
  #define INT_MALI_PP6                AM_IRQ(176)
  #define INT_MALI_PP6_MMU            AM_IRQ(177)
  #define INT_MALI_PP7                AM_IRQ(178)
  #define INT_MALI_PP7_MMU            AM_IRQ(179)

However, the driver from the 3.10 vendor kernel does not use the
following four interrupt lines:
- INT_MALI_PP3
- INT_MALI_PP3_MMU
- INT_MALI_PP7
- INT_MALI_PP7_MMU

Drop the "pp3" and "ppmmu3" interrupt lines. This is also important
because there is no matching entry in interrupt-names for it (meaning
the "pp2" interrupt is actually assigned to the "pp3" interrupt line).

Fixes: 7d3f6b536e72c9 ("ARM: dts: meson8: add the Mali-450 MP6 GPU")
Reported-by: Thomas Graichen 
Signed-off-by: Martin Blumenstingl 
Signed-off-by: Kevin Hilman 
Tested-by: thomas graichen 
Reviewed-by: Neil Armstrong 
Link: https://lore.kernel.org/r/20200815181957.408649-1-martin.blumenstingl@googlemail.com
Signed-off-by: Sasha Levin

ARM: dts: iwg20d-q7-common: Fix touch controller probe failure

2020-10-29T09:12:05+00:00

[ Upstream commit 08d7a73fffb6769b1cf2278bf697e692daba3abf ]

As per the iWave RZ/G1M schematic, the signal LVDS_PPEN controls the
supply voltage for the touch panel, LVDS receiver and RGB LCD panel. Add
a regulator for these device nodes and remove the powerdown-gpios
property from the lvds-receiver node as it results in a touch controller
driver probe failure.

Fixes: 6f89dd9e9325 ("ARM: dts: iwg20d-q7-common: Add LCD support")
Signed-off-by: Biju Das 
Reviewed-by: Laurent Pinchart 
Link: https://lore.kernel.org/r/20200924080535.3641-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven 
Signed-off-by: Sasha Levin

ARM: dts: stm32: Fix DH PDK2 display PWM channel

2020-10-29T09:12:05+00:00

[ Upstream commit 57592d2a98dbc3bde3ddc062e91a8486bdcb211e ]

The display PWM channel is number 3 (PWM2 CH4), make it so.

Fixes: 34e0c7847dcf ("ARM: dts: stm32: Add DH Electronics DHCOM STM32MP1 SoM and PDK2 board")
Signed-off-by: Marek Vasut 
Cc: Alexandre Torgue 
Cc: Maxime Coquelin 
Cc: Patrice Chotard 
Cc: Patrick Delaunay 
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue 
Signed-off-by: Sasha Levin

ARM: dts: stm32: Swap PHY reset GPIO and TSC2004 IRQ on DHCOM SOM

2020-10-29T09:12:05+00:00

[ Upstream commit 9ad98319e95263469d8ca2cb543c37c5a2f40980 ]

On the production revision of the SoM, 587-200, the PHY reset GPIO and
touchscreen IRQs are swapped to prevent collision between EXTi IRQs,
reflect that in DT.

Fixes: 34e0c7847dcf ("ARM: dts: stm32: Add DH Electronics DHCOM STM32MP1 SoM and PDK2 board")
Signed-off-by: Marek Vasut 
Cc: Alexandre Torgue 
Cc: Maxime Coquelin 
Cc: Patrice Chotard 
Cc: Patrick Delaunay 
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue 
Signed-off-by: Sasha Levin

ARM: dts: stm32: Move ethernet PHY into DH SoM DT

2020-10-29T09:12:05+00:00

[ Upstream commit b0a07f609600b6fa4c30f783db50c38456804485 ]

The PHY and the VIO regulator is populated on the SoM, move it
into the SoM DT.

Signed-off-by: Marek Vasut 
Cc: Alexandre Torgue 
Cc: Maxime Coquelin 
Cc: Patrice Chotard 
Cc: Patrick Delaunay 
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue 
Signed-off-by: Sasha Levin

ARM: dts: stm32: lxa-mc1: Fix kernel warning about PHY delays

2020-10-29T09:12:05+00:00

[ Upstream commit 42a31ac6698681363363d48335559d212a26a7ca ]

The KSZ9031 PHY skew timings for rxc/txc, originally set to achieve
the desired phase shift between clock- and data-signal, now trigger a
kernel warning when used in rgmii-id mode:

 *-skew-ps values should be used only with phy-mode = "rgmii"

This is because commit bcf3440c6dd7 ("net: phy: micrel: add phy-mode
support for the KSZ9031 PHY") now configures own timings when
phy-mode = "rgmii-id". Device trees wanting to set their own delays
should use phy-mode "rgmii" instead as the warning prescribes.

The "standard" timings now used with "rgmii-id" work fine on this
board, so drop the explicit timings in the device tree and thereby
silence the warning.

Fixes: 666b5ca85cd3 ("ARM: dts: stm32: add STM32MP1-based Linux Automation MC-1 board")
Signed-off-by: Holger Assmann 
Acked-by: Ahmad Fatoum 
Signed-off-by: Alexandre Torgue 
Signed-off-by: Sasha Levin

ARM: dts: stm32: Fix sdmmc2 pins on AV96

2020-10-29T09:12:05+00:00

[ Upstream commit 1ad6e36ec266cedb0d274aa13253ff1fb2eed4ba ]

The AV96 uses sdmmc2_d47_pins_c and sdmmc2_d47_sleep_pins_c, which
differ from sdmmc2_d47_pins_b and sdmmc2_d47_sleep_pins_b in one
pin, SDMMC2_D5, which is PA15 in the former and PA9 in the later.
The PA15 is correct on AV96, so fix this. This error is likely a
result of rebasing across the stm32mp1 DT pinctrl rework.

Fixes: 611325f68102 ("ARM: dts: stm32: Add eMMC attached to SDMMC2 on AV96")
Signed-off-by: Marek Vasut 
Cc: Alexandre Torgue 
Cc: Maxime Coquelin 
Cc: Patrice Chotard 
Cc: Patrick Delaunay 
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue 
Signed-off-by: Sasha Levin

ARM: OMAP2+: Restore MPU power domain if cpu_cluster_pm_enter() fails

2020-10-29T09:12:04+00:00

[ Upstream commit 8f04aea048d56f3e39a7e543939450246542a6fc ]

If cpu_cluster_pm_enter() fails, we need to set MPU power domain back
to enabled to prevent the next WFI from potentially triggering an
undesired MPU power domain state change.

We already do this for omap_enter_idle_smp() but are missing it for
omap_enter_idle_coupled().

Fixes: 55be2f50336f ("ARM: OMAP2+: Handle errors for cpu_pm")
Signed-off-by: Tony Lindgren 
Signed-off-by: Sasha Levin

ARM: dts: owl-s500: Fix incorrect PPI interrupt specifiers

2020-10-29T09:12:04+00:00

[ Upstream commit 55f6c9931f7c32f19cf221211f099dfd8dab3af9 ]

The PPI interrupts for cortex-a9 were incorrectly specified, fix them.

Fixes: fdfe7f4f9d85 ("ARM: dts: Add Actions Semi S500 and LeMaker Guitar")
Signed-off-by: Cristian Ciocaltea 
Reviewed-by: Peter Korsgaard 
Reviewed-by: Manivannan Sadhasivam 
Signed-off-by: Manivannan Sadhasivam 
Signed-off-by: Sasha Levin

ARM: dts: sun8i: r40: bananapi-m2-ultra: Fix dcdc1 regulator

2020-10-29T09:12:01+00:00

[ Upstream commit 3658a2b7f3e16c7053eb8d70657b94bb62c5a0f4 ]

DCDC1 regulator powers many different subsystems. While some of them can
work at 3.0 V, some of them can not. For example, VCC-HDMI can only work
between 3.24 V and 3.36 V. According to OS images provided by the board
manufacturer this regulator should be set to 3.3 V.

Set DCDC1 and DCDC1SW to 3.3 V in order to fix this.

Fixes: da7ac948fa93 ("ARM: dts: sun8i: Add board dts file for Banana Pi M2 Ultra")
Signed-off-by: Jernej Skrabec 
Signed-off-by: Maxime Ripard 
Link: https://lore.kernel.org/r/20200824193649.978197-1-jernej.skrabec@siol.net
Signed-off-by: Sasha Levin