linux-stable.git/arch/arm64/kernel/cpu_errata.c, branch linux-4.3.y

arm64: KVM: Add workaround for Cortex-A57 erratum 834220

2016-01-31T19:25:55+00:00

commit 498cd5c32be6e32bc0f8efcad48ab094bb2bfdf3 upstream.

Cortex-A57 parts up to r1p2 can misreport Stage 2 translation faults
when a Stage 1 permission fault or device alignment fault should
have been reported.

This patch implements the workaround (which is to validate that the
Stage-1 translation actually succeeds) by using code patching.

Reviewed-by: Will Deacon 
Signed-off-by: Marc Zyngier 
Signed-off-by: Christoffer Dall 
Signed-off-by: Greg Kroah-Hartman

arm64: fix midr range for Cortex-A57 erratum 832075

2015-04-01T10:12:03+00:00

Register MIDR_EL1 is masked to get variant and revision fields, then
compared against midr_range_min and midr_range_max when checking
whether CPU is affected by any particular erratum. However, variant
and revision fields in MIDR_EL1 are separated by 16 bits, so the min
and max of midr range should be constructed accordingly, otherwise
the patch will not be applied when variant field is non-0.

Cc: stable@vger.kernel.org # 3.19+
Acked-by: Andre Przywara 
Reviewed-by: Paul Walmsley 
Signed-off-by: Bo Yan 
[will: use MIDR_VARIANT_SHIFT to construct upper bound]
Signed-off-by: Will Deacon

arm64: errata: add workaround for cortex-a53 erratum #845719

2015-04-01T09:24:31+00:00

When running a compat (AArch32) userspace on Cortex-A53, a load at EL0
from a virtual address that matches the bottom 32 bits of the virtual
address used by a recent load at (AArch64) EL1 might return incorrect
data.

This patch works around the issue by writing to the contextidr_el1
register on the exception return path when returning to a 32-bit task.
This workaround is patched in at runtime based on the MIDR value of the
processor.

Reviewed-by: Marc Zyngier 
Tested-by: Mark Rutland 
Signed-off-by: Will Deacon

arm64: Extract feature parsing code from cpu_errata.c

2015-03-30T10:03:43+00:00

As we detect more architectural features at runtime, it makes
sense to reuse the existing framework whilst avoiding to call
a feature an erratum...

This patch extract the core capability parsing, moves it into
a new file (cpufeature.c), and let the CPU errata detection code
use it.

Reviewed-by: Andre Przywara 
Acked-by: Will Deacon 
Signed-off-by: Marc Zyngier 
Signed-off-by: Will Deacon

arm64: alternatives: fix pr_fmt string for consistency

2014-11-25T18:27:01+00:00

Consistently use the plural form for alternatives pr_fmt strings.

Signed-off-by: Will Deacon

arm64: protect alternatives workarounds with Kconfig options

2014-11-25T15:56:42+00:00

Not all of the errata we have workarounds for apply necessarily to all
SoCs, so people compiling a kernel for one very specific SoC may not
need to patch the kernel.
Introduce a new submenu in the "Platform selection" menu to allow
people to turn off certain bugs if they are not affected. By default
all of them are enabled.
Normal users or distribution kernels shouldn't bother to deselect any
bugs here, since the alternatives framework will take care of
patching them in only if needed.

Signed-off-by: Andre Przywara 
[will: moved kconfig menu under `Kernel Features']
Signed-off-by: Will Deacon

arm64: add Cortex-A57 erratum 832075 workaround

2014-11-25T15:56:42+00:00

The ARM erratum 832075 applies to certain revisions of Cortex-A57,
one of the workarounds is to change device loads into using
load-aquire semantics.
This is achieved using the alternatives framework.

Signed-off-by: Andre Przywara 
Signed-off-by: Will Deacon

arm64: add Cortex-A53 cache errata workaround

2014-11-25T15:56:21+00:00

The ARM errata 819472, 826319, 827319 and 824069 define the same
workaround for these hardware issues in certain Cortex-A53 parts.
Use the new alternatives framework and the CPU MIDR detection to
patch "cache clean" into "cache clean and invalidate" instructions if
an affected CPU is detected at runtime.

Signed-off-by: Andre Przywara 
[will: add __maybe_unused to squash gcc warning]
Signed-off-by: Will Deacon

arm64: detect silicon revisions and set cap bits accordingly

2014-11-25T13:46:37+00:00

After each CPU has been started, we iterate through a list of
CPU features or bugs to detect CPUs which need (or could benefit
from) kernel code patches.
For each feature/bug there is a function which checks if that
particular CPU is affected. We will later provide some more generic
functions for common things like testing for certain MIDR ranges.
We do this for every CPU to cover big.LITTLE systems properly as
well.
If a certain feature/bug has been detected, the capability bit will
be set, so that later the call to apply_alternatives() will trigger
the actual code patching.

Signed-off-by: Andre Przywara 
Signed-off-by: Will Deacon