linux-stable.git/arch/arm/kernel, branch v3.9

ARM: 7699/1: sched_clock: Add more notrace to prevent recursion

2013-04-19T21:23:55+00:00

cyc_to_sched_clock() is called by sched_clock() and cyc_to_ns()
is called by cyc_to_sched_clock(). I suspect that some compilers
inline both of these functions into sched_clock() and so we've
been getting away without having a notrace marking. It seems that
my compiler isn't inlining cyc_to_sched_clock() though, so I'm
hitting a recursion bug when I enable the function graph tracer,
causing my system to crash. Marking these functions notrace fixes
it. Technically cyc_to_ns() doesn't need the notrace because it's
already marked inline, but let's just add it so that if we ever
remove inline from that function it doesn't blow up.

Signed-off-by: Stephen Boyd 
Signed-off-by: Russell King

ARM: 7698/1: perf: fix group validation when using enable_on_exec

2013-04-17T15:54:07+00:00

Events may be created with attr->disabled == 1 and attr->enable_on_exec
== 1, which confuses the group validation code because events with the
PERF_EVENT_STATE_OFF are not considered candidates for scheduling, which
may lead to failure at group scheduling time.

This patch fixes the validation check for ARM, so that events in the
OFF state are still considered when enable_on_exec is true.

Cc: stable@vger.kernel.org
Cc: Peter Zijlstra 
Cc: Arnaldo Carvalho de Melo 
Cc: Jiri Olsa 
Reported-by: Sudeep KarkadaNagesha 
Signed-off-by: Will Deacon 
Signed-off-by: Russell King

ARM: 7697/1: hw_breakpoint: do not use __cpuinitdata for dbg_cpu_pm_nb

2013-04-17T15:54:06+00:00

We must not declare dbg_cpu_pm_nb as __cpuinitdata as we need it after
system initialization for Suspend and CPUIdle.

This was done in commit 9a6eb310eaa5 ("ARM: hw_breakpoint: Debug powerdown
support for self-hosted debug").

Cc: stable@vger.kernel.org
Cc: Dietmar Eggemann 
Signed-off-by: Bastian Hecht 
Signed-off-by: Will Deacon 
Signed-off-by: Russell King

ARM: 7694/1: ARM, TCM: initialize TCM in paging_init(), instead of setup_arch()

2013-04-17T15:53:24+00:00

tcm_init() call iotable_init() and it use early_alloc variants which
do memblock allocation. Directly using memblock allocation after
initializing bootmem should not permitted, because bootmem can't know
where are additinally reserved.
So move tcm_init() to a safe place before initalizing bootmem.

(On the U300)

Tested-by: Linus Walleij 
Signed-off-by: Joonsoo Kim 
Signed-off-by: Russell King

ARM: 7690/1: mm: fix CONFIG_LPAE typos

2013-04-03T15:45:51+00:00

CONFIG_LPAE doesn't exist: the correct option is CONFIG_ARM_LPAE, so fix
up the two typos under arch/arm/.

The fix to head.S is slightly scary, but this is just for setting up
an early io-mapping for the serial port when running on a big-endian,
LPAE system. Since these systems don't exist in the wild (at least, I
have no access to one outside of kvmtool, which doesn't provide a serial
port suitable for earlyprintk), then we can revisit the code later if it
causes any problems.

Signed-off-by: Paul Bolle 
Signed-off-by: Will Deacon 
Signed-off-by: Russell King

ARM: 7689/1: add unwind annotations to ftrace asm

2013-04-03T15:45:50+00:00

Add unwind annotations to the ftrace assembly code so that the function
tracer's stacktracing options (func_stack_trace, etc.) work when
CONFIG_ARM_UNWIND is enabled.

Signed-off-by: Rabin Vincent 
Signed-off-by: Russell King

ARM: 7685/1: delay: use private ticks_per_jiffy field for timer-based delay ops

2013-04-03T15:45:50+00:00

Commit 70264367a243 ("ARM: 7653/2: do not scale loops_per_jiffy when
using a constant delay clock") fixed a problem with our timer-based
delay loop, where loops_per_jiffy is scaled by cpufreq yet used directly
by the timer delay ops.

This patch fixes the problem in a more elegant way by keeping a private
ticks_per_jiffy field in the delay ops, independent of loops_per_jiffy
and therefore not subject to scaling. The loop-based delay continues to
use loops_per_jiffy directly, as it should.

Acked-by: Nicolas Pitre 
Signed-off-by: Will Deacon 
Signed-off-by: Russell King

ARM: 7684/1: errata: Workaround for Cortex-A15 erratum 798181 (TLBI/DSB operations)

2013-04-03T15:45:49+00:00

On Cortex-A15 (r0p0..r3p2) the TLBI/DSB are not adequately shooting down
all use of the old entries. This patch implements the erratum workaround
which consists of:

1. Dummy TLBIMVAIS and DSB on the CPU doing the TLBI operation.
2. Send IPI to the CPUs that are running the same mm (and ASID) as the
   one being invalidated (or all the online CPUs for global pages).
3. CPU receiving the IPI executes a DMB and CLREX (part of the exception
   return code already).

Signed-off-by: Catalin Marinas 
Signed-off-by: Russell King

ARM: 7681/1: hw_breakpoint: use warn_once to avoid spam from reset_ctrl_regs()

2013-03-22T17:16:56+00:00

CPU debug features like hardware break, watchpoints can be used only
when the debug mode is enabled and available. Unfortunately on OMAP4
based devices, after a CPU power cycle, the debug feature gets disabled
which leads to a flood of messages coming from reset_ctrl_regs() which
gets called on every CPU_PM_EXIT with CPUidle enabled.

So make use of warn_once() so that system is usable.

Thanks to Will for pointers and Lokesh for the analysis of the issue.

Tested-by: Lokesh Vutla 
Signed-off-by: Santosh Shilimkar 
Signed-off-by: Will Deacon 
Signed-off-by: Russell King

ARM: 7680/1: Detect support for SDIV/UDIV from ISAR0 register

2013-03-22T17:16:55+00:00

The ISAR0 register indicates support for the SDIV and UDIV
instructions in both the Thumb and ARM instruction set. Read the
register to detect the supported instructions and update the
elf_hwcap mask as appropriate. This is better than adding more
and more cpuid checks in proc-v7.S for each new cpu variant that
supports these instructions.

Acked-by: Will Deacon 
Cc: Stepan Moskovchenko 
Signed-off-by: Stephen Boyd 
Signed-off-by: Russell King