linux-stable.git/arch/arm/kernel/setup.c, branch v4.12.2

ARM: 8682/1: V7M: Set cacheid iff DminLine or IminLine is nonzero

2017-06-12T14:47:29+00:00

Cache support is optional feature in M-class cores, thus DminLine or
IminLine of Cache Type Register is zero if caches are not implemented,
but we check the whole CTR which has other features encoded there.
Let's be more precise and check for DminLine and IminLine of CTR
before we set cacheid.

Signed-off-by: Vladimir Murzin 
Signed-off-by: Russell King

ARM: 8667/3: Fix memory attribute inconsistencies when using fixmap

2017-04-20T10:19:42+00:00

To cope with the variety in ARM architectures and configurations, the
pagetable attributes for kernel memory are generated at runtime to match
the system the kernel finds itself on. This calculated value is stored
in pgprot_kernel.

However, when early fixmap support was added for ARM (commit
a5f4c561b3b1) the attributes used for mappings were hard coded because
pgprot_kernel is not set up early enough. Unfortunately, when fixmap is
used after early boot this means the memory being mapped can have
different attributes to existing mappings, potentially leading to
unpredictable behaviour. A specific problem also exists due to the hard
coded values not include the 'shareable' attribute which means on
systems where this matters (e.g. those with multiple CPU clusters) the
cache contents for a memory location can become inconsistent between
CPUs.

To resolve these issues we change fixmap to use the same memory
attributes (from pgprot_kernel) that the rest of the kernel uses. To
enable this we need to refactor the initialisation code so
build_mem_type_table() is called early enough. Note, that relies on early
param parsing for memory type overrides passed via the kernel command
line, so we need to make sure this call is still after
parse_early_params().

[ardb: keep early_fixmap_init() before param parsing, for earlycon]

Fixes: a5f4c561b3b1 ("ARM: 8415/1: early fixmap support for earlycon")
Cc:  # v4.3+
Tested-by: afzal mohammed 
Signed-off-by: Jon Medhurst 
Signed-off-by: Ard Biesheuvel 
Signed-off-by: Russell King

ARM: 8637/1: Adjust memory boundaries after reservations

2017-02-28T11:05:28+00:00

adjust_lowmem_bounds is responsible for setting up the boundary for
lowmem/highmem. This needs to be setup before memblock reservations can
occur. At the time memblock reservations can occur, memory can also be
removed from the system. The lowmem/highmem boundary and end of memory
may be affected by this but it is currently not recalculated. On some
systems this may be harmless, on others this may result in incorrect
ranges being passed to the main memory allocator. Correct this by
recalculating the lowmem/highmem boundary after all reservations have
been made.

Tested-by: Magnus Lilja 
Signed-off-by: Laura Abbott 
Signed-off-by: Russell King

ARM: 8636/1: Cleanup sanity_check_meminfo

2017-02-28T11:04:57+00:00

The logic for sanity_check_meminfo has become difficult to
follow. Clean up the code so it's more obvious what the code
is actually trying to do. Additionally, meminfo is now removed
so rename the function to better describe its purpose.

Tested-by: Magnus Lilja 
Reviewed-by: Nicolas Pitre 
Signed-off-by: Laura Abbott 
Signed-off-by: Laura Abbott 
Signed-off-by: Russell King

ARM: 8604/1: V7M: Add support for reading the CTR with read_cpuid_cachetype()

2016-09-06T14:51:07+00:00

With the addition of caches to the V7M Architecture a new Cache Type
Register (CTR) is defined at 0xE000ED7C. This register serves the same
purpose as the V7A/R version and accessed via the read_cpuid_cachetype.

Signed-off-by: Jonathan Austin 
Signed-off-by: Vladimir Murzin 
Tested-by: Andras Szemzo 
Tested-by: Joachim Eastwood 
Tested-by: Alexandre TORGUE 
Signed-off-by: Russell King

ARM: 8602/1: factor out CSSELR/CCSIDR operations that use cp15 directly

2016-09-06T14:51:06+00:00

Currently we use raw cp15 operations to access the cache setup data.

This patch abstracts the CSSELR and CCSIDR accessors out to a header so
that the implementation for them can be switched out as we do with other
cpu/cachetype operations.

Signed-off-by: Jonathan Austin 
Signed-off-by: Vladimir Murzin 
Tested-by: Andras Szemzo 
Tested-by: Joachim Eastwood 
Tested-by: Alexandre TORGUE 
Signed-off-by: Russell King

ARM: 8595/2: apply more __ro_after_init

2016-08-12T15:47:06+00:00

Guided by grsecurity's analogous __read_only markings in arch/arm,
this applies several uses of __ro_after_init to structures that are
only updated during __init.

Signed-off-by: Kees Cook 
Signed-off-by: Russell King

ARM: kexec: advertise location of bootable RAM

2016-08-02T23:35:25+00:00

Advertise the location of bootable RAM to kexec-tools.  kexec needs to
know where it can place the kernel in RAM, and so be executable when the
system needs to jump into it.

Advertise these areas in /proc/iomem with a "System RAM (boot alias)"
tag.

Link: http://lkml.kernel.org/r/E1b8ko4-0004HA-GF@rmk-PC.armlinux.org.uk
Signed-off-by: Russell King 
Reviewed-by: Pratyush Anand 
Cc: Baoquan He 
Cc: Keerthy 
Cc: Vitaly Andrianov 
Cc: Eric Biederman 
Cc: Dave Young 
Cc: Vivek Goyal 
Cc: Simon Horman 
Signed-off-by: Andrew Morton 
Signed-off-by: Linus Torvalds

ARM: kdump: advertise boot aliased crash kernel resource

2016-08-02T23:35:25+00:00

Advertise a resource which describes where the crash kernel is located
in the boot view of RAM.  This allows kexec-tools to have this vital
information.

Link: http://lkml.kernel.org/r/E1b8knz-0004H4-Bd@rmk-PC.armlinux.org.uk
Signed-off-by: Russell King 
Cc: Baoquan He 
Cc: Keerthy 
Cc: Pratyush Anand 
Cc: Vitaly Andrianov 
Cc: Eric Biederman 
Cc: Dave Young 
Cc: Vivek Goyal 
Cc: Simon Horman 
Signed-off-by: Andrew Morton 
Signed-off-by: Linus Torvalds

Merge tag 'devicetree-for-4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux

2016-07-30T18:32:01+00:00

Pull DeviceTree updates from Rob Herring:

 - remove most of_platform_populate() calls in arch code.  Now the DT
   core code calls it in the default case and platforms only need to
   call it if they have special needs

 - use pr_fmt on all the DT core print statements

 - CoreSight binding doc improvements to block name descriptions

 - add dt_to_config script which can parse dts files and list
   corresponding kernel config options

 - fix memory leak hit with a PowerMac DT

 - correct a bunch of STMicro compatible strings to use the correct
   vendor prefix

 - fix DA9052 PMIC binding doc to match what is actually used in dts
   files

* tag 'devicetree-for-4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (35 commits)
  documentation: da9052: Update regulator bindings names to match DA9052/53 DTS expectations
  xtensa: Partially Revert "xtensa: Remove unnecessary of_platform_populate with default match table"
  xtensa: Fix build error due to missing include file
  MIPS: ath79: Add missing include file
  Fix spelling errors in Documentation/devicetree
  ARM: dts: fix STMicroelectronics compatible strings
  powerpc/dts: fix STMicroelectronics compatible strings
  Documentation: dt: i2c: use correct STMicroelectronics vendor prefix
  scripts/dtc: dt_to_config - kernel config options for a devicetree
  of: fdt: mark unflattened tree as detached
  of: overlay: add resolver error prints
  coresight: document binding acronyms
  Documentation/devicetree: document cavium-pip rx-delay/tx-delay properties
  of: use pr_fmt prefix for all console printing
  of/irq: Mark initialised interrupt controllers as populated
  of: fix memory leak related to safe_name()
  Revert "of/platform: export of_default_bus_match_table"
  of: unittest: use of_platform_default_populate() to populate default bus
  memory: omap-gpmc: use of_platform_default_populate() to populate default bus
  bus: uniphier-system-bus: use of_platform_default_populate() to populate default bus
  ...