linux-stable.git/arch/arm/kernel/setup.c, branch v3.18.76 Linux kernel stable tree Revert "ARM: 7830/1: delay: don't bother reporting bogomips in /proc/cpuinfo" 2015-01-16T14:59:55+00:00 Pavel Machek pavel@ucw.cz 2015-01-04T19:01:23+00:00 713beaa02f51ab8c69c13e6a416e1b500363d780 commit 4bf9636c39ac70da091d5a2e28d3448eaa7f115c upstream. Commit 9fc2105aeaaf ("ARM: 7830/1: delay: don't bother reporting bogomips in /proc/cpuinfo") breaks audio in python, and probably elsewhere, with message FATAL: cannot locate cpu MHz in /proc/cpuinfo I'm not the first one to hit it, see for example https://theredblacktree.wordpress.com/2014/08/10/fatal-cannot-locate-cpu-mhz-in-proccpuinfo/ https://devtalk.nvidia.com/default/topic/765800/workaround-for-fatal-cannot-locate-cpu-mhz-in-proc-cpuinf/?offset=1 Reading original changelog, I have to say "Stop breaking working setups. You know who you are!". Signed-off-by: Pavel Machek <pavel@ucw.cz> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> 
commit 4bf9636c39ac70da091d5a2e28d3448eaa7f115c upstream.

Commit 9fc2105aeaaf ("ARM: 7830/1: delay: don't bother reporting
bogomips in /proc/cpuinfo") breaks audio in python, and probably
elsewhere, with message

  FATAL: cannot locate cpu MHz in /proc/cpuinfo

I'm not the first one to hit it, see for example

  https://theredblacktree.wordpress.com/2014/08/10/fatal-cannot-locate-cpu-mhz-in-proccpuinfo/
  https://devtalk.nvidia.com/default/topic/765800/workaround-for-fatal-cannot-locate-cpu-mhz-in-proc-cpuinf/?offset=1

Reading original changelog, I have to say "Stop breaking working setups.
You know who you are!".

Signed-off-by: Pavel Machek <pavel@ucw.cz>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
ARM: 8150/3: fiq: Replace default FIQ handler 2014-09-17T23:35:18+00:00 Daniel Thompson daniel.thompson@linaro.org 2014-09-17T16:12:06+00:00 c0e7f7ee717e2b4c5791e7422424c96b5008c39e This patch introduces a new default FIQ handler that is structured in a similar way to the existing ARM exception handler and result in the FIQ being handled by C code running on the SVC stack (despite this code run in the FIQ handler is subject to severe limitations with respect to locking making normal interaction with the kernel impossible). This default handler allows concepts that on x86 would be handled using NMIs to be realized on ARM. Credit: This patch is a near complete re-write of a patch originally provided by Anton Vorontsov. Today only a couple of small fragments survive, however without Anton's work to build from this patch would not exist. Thanks also to Russell King for spoonfeeding me a variety of fixes during the review cycle. Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org> Cc: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 
This patch introduces a new default FIQ handler that is structured in a
similar way to the existing ARM exception handler and result in the FIQ
being handled by C code running on the SVC stack (despite this code run
in the FIQ handler is subject to severe limitations with respect to
locking making normal interaction with the kernel impossible).

This default handler allows concepts that on x86 would be handled using
NMIs to be realized on ARM.

Credit:

    This patch is a near complete re-write of a patch originally
    provided by Anton Vorontsov. Today only a couple of small fragments
    survive, however without Anton's work to build from this patch would
    not exist. Thanks also to Russell King for spoonfeeding me a variety
    of fixes during the review cycle.

Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
ARM: hwcap: disable HWCAP_SWP if the CPU advertises it has exclusives 2014-07-18T11:29:51+00:00 Russell King rmk+kernel@arm.linux.org.uk 2014-07-04T15:41:21+00:00 58171bf2af6b547a560b304f6ab2b9edf1c31d5a When the CPU has support for the byte and word exclusive operations, userspace should use them in preference to the SWP instructions. Detect the presence of these instructions by reading the ISAR CPU ID registers and adjust the ELF HWCAP mask appropriately. Note that ARM1136 < r1p0 has no ISAR4, so this is explicitly detected and the test disabled, leaving the current situation where HWCAP_SWP is set. Tested-by: Tony Lindgren <tony@atomide.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 
When the CPU has support for the byte and word exclusive operations,
userspace should use them in preference to the SWP instructions.
Detect the presence of these instructions by reading the ISAR CPU ID
registers and adjust the ELF HWCAP mask appropriately.

Note that ARM1136 < r1p0 has no ISAR4, so this is explicitly detected
and the test disabled, leaving the current situation where HWCAP_SWP
is set.

Tested-by: Tony Lindgren <tony@atomide.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Merge branches 'alignment', 'fixes', 'l2c' (early part) and 'misc' into for-next 2014-06-05T11:35:52+00:00 Russell King rmk+kernel@arm.linux.org.uk 2014-06-05T11:35:52+00:00 1fb333489fb917c704ad43e51b45c12f52215a9c 






ARM: ensure C page table setup code follows assembly code
2014-06-02T08:23:54+00:00

Russell King
rmk+kernel@arm.linux.org.uk

2014-05-27T19:34:28+00:00

ca8f0b0a545f55b3dc6877cda24d609a8979c951

Fix a long standing bug where, for ARMv6+, we don't fully ensure that
the C code sets the same cache policy as the assembly code.  This was
introduced partially by commit 11179d8ca28d ([ARM] 4497/1: Only allow
safe cache configurations on ARMv6 and later) and also by adding SMP
support.

This patch sets the default cache policy based on the flags used by the
assembly code, and then ensures that when a cache policy command line
argument is used, we verify that on ARMv6, it matches the initial setup.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>





Fix a long standing bug where, for ARMv6+, we don't fully ensure that
the C code sets the same cache policy as the assembly code.  This was
introduced partially by commit 11179d8ca28d ([ARM] 4497/1: Only allow
safe cache configurations on ARMv6 and later) and also by adding SMP
support.

This patch sets the default cache policy based on the flags used by the
assembly code, and then ensures that when a cache policy command line
argument is used, we verify that on ARMv6, it matches the initial setup.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>







ARM: 8025/1: Get rid of meminfo
2014-06-01T00:17:12+00:00

Laura Abbott
lauraa@codeaurora.org

2014-04-13T21:54:58+00:00

1c2f87c22566cd057bc8cde10c37ae9da1a1bb76

memblock is now fully integrated into the kernel and is the prefered
method for tracking memory. Rather than reinvent the wheel with
meminfo, migrate to using memblock directly instead of meminfo as
an intermediate.

Acked-by: Jason Cooper <jason@lakedaemon.net>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Tested-by: Leif Lindholm <leif.lindholm@linaro.org>
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>





memblock is now fully integrated into the kernel and is the prefered
method for tracking memory. Rather than reinvent the wheel with
meminfo, migrate to using memblock directly instead of meminfo as
an intermediate.

Acked-by: Jason Cooper <jason@lakedaemon.net>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Tested-by: Leif Lindholm <leif.lindholm@linaro.org>
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>







ARM: use get_cr() rather than cr_alignment
2014-05-22T15:27:27+00:00

Russell King
rmk+kernel@arm.linux.org.uk

2014-04-13T17:47:34+00:00

4585eaff634b1bbb09686895221b3645f53f7a60

Rather than reading the cr_alignment variable, use get_cr() to read
directly from the hardware instead.  We have two places where this
occurs, neither of them are performance critical.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>





Rather than reading the cr_alignment variable, use get_cr() to read
directly from the hardware instead.  We have two places where this
occurs, neither of them are performance critical.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>







Merge branches 'amba', 'fixes', 'misc', 'mmci', 'unstable/omap-dma' and 'unstable/sa11x0' into for-next
2014-04-03T23:33:32+00:00

Russell King
rmk+kernel@arm.linux.org.uk

2014-04-03T23:33:32+00:00

95959e6a06720834fc80a210e37898341c63cb91












ARM: 7982/1: introduce HWCAP2 feature bits for ARMv8 Crypto Extensions
2014-02-25T11:40:50+00:00

Ard Biesheuvel
ard.biesheuvel@linaro.org

2014-02-19T21:29:40+00:00

8258a9895c99cdaacad8edc4748c0a624c710961

This allocates feature bits 0-4 in HWCAP2 for the crypto and CRC
extensions introduced in ARMv8.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>





This allocates feature bits 0-4 in HWCAP2 for the crypto and CRC
extensions introduced in ARMv8.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>







ARM: 7981/1: add support for AT_HWCAP2 ELF auxv entry
2014-02-25T11:40:48+00:00

Ard Biesheuvel
ard.biesheuvel@linaro.org

2014-02-19T21:28:40+00:00

b342ea4e4ff970518264c81eefd05f637e3f193a

This enables AT_HWCAP2 for ARM. The generic support for this
new ELF auxv entry was added in commit 2171364d1a9 (powerpc:
Add HWCAP2 aux entry)

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>





This enables AT_HWCAP2 for ARM. The generic support for this
new ELF auxv entry was added in commit 2171364d1a9 (powerpc:
Add HWCAP2 aux entry)

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>