linux-stable.git/arch/arm/kernel/entry-header.S, branch linux-3.4.y

ARM: 8129/1: errata: work around Cortex-A15 erratum 830321 using dummy strex

2014-09-25T03:49:16+00:00

commit 2c32c65e3726c773760038910be30cce1b4d4149 upstream.

On revisions of Cortex-A15 prior to r3p3, a CLREX instruction at PL1 may
falsely trigger a watchpoint exception, leading to potential data aborts
during exception return and/or livelock.

This patch resolves the issue in the following ways:

  - Replacing our uses of CLREX with a dummy STREX sequence instead (as
    we did for v6 CPUs).

  - Removing the clrex code from v7_exit_coherency_flush and derivatives,
    since this only exists as a minor performance improvement when
    non-cached exclusives are in use (Linux doesn't use these).

Benchmarking on a variety of ARM cores revealed no measurable
performance difference with this change applied, so the change is
performed unconditionally and no new Kconfig entry is added.

Signed-off-by: Mark Rutland 
Signed-off-by: Will Deacon 
Signed-off-by: Russell King 
[lizf: Backported to 3.4:
 - Drop changes to arch/arm/include/asm/cacheflush.h and
   arch/arm/mach-exynos/mcpm-exynos.c]
Signed-off-by: Zefan Li

Merge branch 'devel-stable' into for-next

2011-07-22T22:09:07+00:00

Conflicts:
	arch/arm/kernel/entry-armv.S

ARM: Thumb-2: Fix exception return sequence to restore stack correctly

2011-07-13T17:32:40+00:00

The implementation of svc_exit didn't take into account any stack hole
created by svc_entry; as happens with the undef handler when kprobes are
configured. The fix is to read the saved value of SP rather than trying
to calculate it.

Signed-off-by: Jon Medhurst 
Acked-by: Nicolas Pitre

ARM: entry: avoid enabling interrupts in prefetch/data abort handlers

2011-07-02T09:56:00+00:00

Avoid enabling interrupts if the parent context had interrupts enabled
in the abort handler assembly code, and move this into the breakpoint/
page/alignment fault handlers instead.

This gets rid of some special-casing for the breakpoint fault handlers
from the low level abort handler path.

Acked-by: Will Deacon 
Signed-off-by: Russell King

ARM: v6k: select clear exclusive code seqences according to V6 variants

2011-02-02T21:23:28+00:00

If CONFIG_CPU_V6 is enabled, then the kernel must support ARMv6 CPUs
which don't have the V6K extensions implemented.  Always use the
dummy store-exclusive method to ensure that the exclusive monitors are
cleared.

If CONFIG_CPU_V6 is not set, but CONFIG_CPU_32v6K is enabled, then we
have the K extensions available on all CPUs we're building support for,
so we can use the new clear-exclusive instruction.

Acked-by: Tony Lindgren 
Tested-by: Sourav Poddar 
Tested-by: Will Deacon 
Signed-off-by: Russell King

ARM: hw_breakpoint: disable preemption during debug exception handling

2010-12-06T11:55:56+00:00

On ARM, debug exceptions occur in the form of data or prefetch aborts.
One difference is that debug exceptions require access to per-cpu banked
registers and data structures which are not saved in the low-level exception
code. For kernels built with CONFIG_PREEMPT, there is an unlikely scenario
that the debug handler ends up running on a different CPU from the one
that originally signalled the event, resulting in random data being read
from the wrong registers.

This patch adds a debug_entry macro to the low-level exception handling
code which checks whether the taken exception is a debug exception. If
it is, the preempt count for the faulting process is incremented. After
the debug handler has finished, the count is decremented.

Acked-by: Catalin Marinas 
Signed-off-by: Will Deacon

ARM: 5991/1: Fix regression in restore_user_regs macro

2010-03-15T17:20:08+00:00

ARMv5T and earlier require that a ldm {}^ instruction is not followed
by an instruction that accesses banked registers. This patch restores
the nop that was lost in commit b86040a59feb255a8193173caa4d5199464433d5.

Signed-off-by: Anders Grafström 
Signed-off-by: Russell King

ARM: 5757/1: Thumb-2: Correct "mov.w pc, lr" instruction which is unpredictable

2009-10-14T09:33:05+00:00

The 32-bit wide variant of "mov pc, reg" in Thumb-2 is unpredictable
causing improper handling of the undefined instructions not caught by
the kernel. This patch adds a movw_pc macro for such situations
(currently only used in call_fpe).

Signed-off-by: Catalin Marinas 
Signed-off-by: Russell King

make Linux bootable on ARM again

2009-09-26T17:06:53+00:00

Commit 200b812d00 "Clear the exclusive monitor when returning from an
exception" broke the vast majority of ARM systems in the wild which are
still pre ARMv6.  The kernel is crashing on the first occurrence of an
exception due to the removal of the actual return instruction for them.
Let's add it back.

Signed-off-by: Nicolas Pitre 
Acked-by: Uwe Kleine-König 
Signed-off-by: Linus Torvalds

Clear the exclusive monitor when returning from an exception

2009-09-18T22:30:11+00:00

The patch adds a CLREX or dummy STREX to the exception return path. This
is needed because several atomic/locking operations use a pair of
LDREX/STREXEQ and the EQ condition may not always be satisfied. This
would leave the exclusive monitor status set and may cause problems with
atomic/locking operations in the interrupted code.

With this patch, the atomic_set() operation can be a simple STR
instruction (on SMP systems, the global exclusive monitor is cleared by
STR anyway). Clearing the exclusive monitor during context switch is no
longer needed as this is handled by the exception return path anyway.

Signed-off-by: Catalin Marinas 
Reported-by: Jamie Lokier