linux-stable.git/arch/arm/kernel/entry-common.S, branch v4.1

ARM: fix missing syscall trace exit

2015-05-15T10:06:35+00:00

Josh Stone reports:

  I've discovered a case where both arm and arm64 will miss a ptrace
  syscall-exit that they should report.  If the syscall is entered
  without TIF_SYSCALL_TRACE set, then it goes on the fast path.  It's
  then possible to have TIF_SYSCALL_TRACE added in the middle of the
  syscall, but ret_fast_syscall doesn't check this flag again.

Fix this by always checking for a syscall trace in the fast exit path.

Reported-by: Josh Stone 
Signed-off-by: Russell King

ARM: move ftrace assembly code to separate file

2014-11-21T15:25:01+00:00

The ftrace assembly code doesn't need to live in entry-common.S and
be surrounded with #ifdef CONFIG_FUNCTION_TRACER.  Instead, move it
to its own file and conditionally assemble it.

Tested-by: Felipe Balbi 
Signed-off-by: Russell King

ARM: Avoid writing to control register on every exception

2014-09-26T13:39:54+00:00

If we are not changing the control register value, avoid writing to it.
Writes to the control register can be very expensive, taking around a
hundred cycles or so.

Signed-off-by: Russell King

ARM: convert all "mov.* pc, reg" to "bx reg" for ARMv6+

2014-07-18T11:29:04+00:00

ARMv6 and greater introduced a new instruction ("bx") which can be used
to return from function calls.  Recent CPUs perform better when the
"bx lr" instruction is used rather than the "mov pc, lr" instruction,
and this sequence is strongly recommended to be used by the ARM
architecture manual (section A.4.1.1).

We provide a new macro "ret" with all its variants for the condition
code which will resolve to the appropriate instruction.

Rather than doing this piecemeal, and miss some instances, change all
the "mov pc" instances to use the new macro, with the exception of
the "movs" instruction and the kprobes code.  This allows us to detect
the "mov pc, lr" case and fix it up - and also gives us the possibility
of deploying this for other registers depending on the CPU selection.

Reported-by: Will Deacon 
Tested-by: Stephen Warren  # Tegra Jetson TK1
Tested-by: Robert Jarzmik  # mioa701_bootresume.S
Tested-by: Andrew Lunn  # Kirkwood
Tested-by: Shawn Guo 
Tested-by: Tony Lindgren  # OMAPs
Tested-by: Gregory CLEMENT  # Armada XP, 375, 385
Acked-by: Sekhar Nori  # DaVinci
Acked-by: Christoffer Dall  # kvm/hyp
Acked-by: Haojian Zhuang  # PXA3xx
Acked-by: Stefano Stabellini  # Xen
Tested-by: Uwe Kleine-König  # ARMv7M
Tested-by: Simon Horman  # Shmobile
Signed-off-by: Russell King

ARM: consolidate last remaining open-coded alignment trap enable

2014-06-02T08:20:20+00:00

We can use the alignment_trap assembly macro here too.

Signed-off-by: Russell King

ARM: asm: Add ARM_BE8() assembly helper

2013-10-19T19:46:33+00:00

Add ARM_BE8() helper to wrap any code conditional on being
compile when CONFIG_ARM_ENDIAN_BE8 is selected and convert
existing places where this is to use it.

Acked-by: Nicolas Pitre 
Reviewed-by: Will Deacon 
Signed-off-by: Ben Dooks

ARM: 7839/1: entry: fix tracing of ARM-private syscalls

2013-09-21T19:41:25+00:00

Commit 377747c40657 ("ARM: entry: allow ARM-private syscalls to be
restarted") reworked the low-level syscall dispatcher to allow
restarting of ARM-private syscalls. Unfortunately, this relocated the
label used to dispatch a private syscall from the trace path, so that
the invocation would be bypassed altogether!

This causes applications to fail under strace as soon as they rely on
a private syscall (e.g. set_tls):

  set_tls(0xb6fad4c0, 0xb6fadb98, 0xb6fb1050, 0xb6fad4c0, 0xb6fb1050)
      = -1 ENOSYS (Function not implemented)

This patch fixes the label so that we correctly dispatch private
syscalls from the trace path.

Reported-by: Jason Gunthorpe 
Tested-by: Jason Gunthorpe 
Signed-off-by: Will Deacon 
Signed-off-by: Russell King

ARM: entry: allow ARM-private syscalls to be restarted

2013-07-22T09:49:00+00:00

System calls will only be restarted after signal handling if they (a)
return an error code indicating that a restart is required and (b) have
`why' set to a non-zero value, to indicate that the signal interrupted
them.

This patch leaves `why' set to a non-zero value for ARM-private syscalls
, and only zeroes it for syscalls that are not implemented.

Signed-off-by: Will Deacon

Merge branch 'devel-stable' into for-next

2013-06-29T10:44:43+00:00

Conflicts:
	arch/arm/Makefile
	arch/arm/include/asm/glue-proc.h

ARM: 7748/1: oabi: handle faults when loading swi instruction from userspace

2013-06-17T08:27:02+00:00

Running an OABI_COMPAT kernel on an SMP platform can lead to fun and
games with page aging.

If one CPU issues a swi instruction immediately before another CPU
decides to mkold the page containing the swi instruction, then we will
fault attempting to load the instruction during the vector_swi handler
in order to retrieve its immediate field. Since this fault is not
currently dealt with by our exception tables, this results in a panic:

  Unable to handle kernel paging request at virtual address 4020841c
  pgd = c490c000
  [4020841c] *pgd=84451831, *pte=bf05859d, *ppte=00000000
  Internal error: Oops: 17 [#1] PREEMPT SMP ARM
  Modules linked in: hid_sony(O)
  CPU: 1    Tainted: G        W  O  (3.4.0-perf-gf496dca-01162-gcbcc62b #1)
  PC is at vector_swi+0x28/0x88
  LR is at 0x40208420

This patch wraps all of the swi instruction loads with the USER macro
and provides a shared exception table entry which simply rewinds the
saved user PC and returns from the system call (without setting tbl, so
there's no worries with tracing or syscall restarting). Returning to
userspace will re-enter the page fault handler, from where we will
probably send SIGSEGV to the current task.

Reported-by: Wang, Yalin 
Reviewed-by: Nicolas Pitre 
Signed-off-by: Will Deacon 
Signed-off-by: Russell King