<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-stable.git/arch/arm/include, branch v2.6.38</title>
<subtitle>Linux kernel stable tree</subtitle>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/'/>
<entry>
<title>ARM: 6765/1: remove obsolete comment from asm/mach/arch.h</title>
<updated>2011-02-26T13:33:47+00:00</updated>
<author>
<name>Nicolas Pitre</name>
<email>nicolas.pitre@linaro.org</email>
</author>
<published>2011-02-24T21:57:14+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=8f3112707fabc2f9f932a4ac1c5b92f3266e4662'/>
<id>8f3112707fabc2f9f932a4ac1c5b92f3266e4662</id>
<content type='text'>
Since commit 6fc31d54 this comment is no longer true.

Signed-off-by: Nicolas Pitre &lt;nicolas.pitre@linaro.org&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Since commit 6fc31d54 this comment is no longer true.

Signed-off-by: Nicolas Pitre &lt;nicolas.pitre@linaro.org&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: 6757/1: fix tlb.h induced linux/swap.h build failure</title>
<updated>2011-02-23T16:19:21+00:00</updated>
<author>
<name>Uwe Kleine-König</name>
<email>u.kleine-koenig@pengutronix.de</email>
</author>
<published>2011-02-22T22:29:37+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=97594b0f35c0708cb9551c070b9693a52ec24ebf'/>
<id>97594b0f35c0708cb9551c070b9693a52ec24ebf</id>
<content type='text'>
Commit

	06824ba (ARM: tlb: delay page freeing for SMP and ARMv7 CPUs)

introduced a build failure for builds with CONFIG_SWAP=n:

	In file included from arch/arm/mm/init.c:27:
	arch/arm/include/asm/tlb.h: In function 'tlb_flush_mmu':
	arch/arm/include/asm/tlb.h:101: error: implicit declaration of function 'release_pages'
	arch/arm/include/asm/tlb.h: In function 'tlb_remove_page':
	arch/arm/include/asm/tlb.h:165: error: implicit declaration of function 'page_cache_release'

as linux/swap.h doesn't include linux/pagemap.h but actually needs it
(see comments in linux/swap.h as to why this is.)

Fix that by #including &lt;linux/pagemap.h&gt; in &lt;asm/pgalloc.h&gt; as it's done
by x86.

Signed-off-by: Uwe Kleine-König &lt;u.kleine-koenig@pengutronix.de&gt;
Acked-by: Tony Lindgren &lt;tony@atomide.com&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Commit

	06824ba (ARM: tlb: delay page freeing for SMP and ARMv7 CPUs)

introduced a build failure for builds with CONFIG_SWAP=n:

	In file included from arch/arm/mm/init.c:27:
	arch/arm/include/asm/tlb.h: In function 'tlb_flush_mmu':
	arch/arm/include/asm/tlb.h:101: error: implicit declaration of function 'release_pages'
	arch/arm/include/asm/tlb.h: In function 'tlb_remove_page':
	arch/arm/include/asm/tlb.h:165: error: implicit declaration of function 'page_cache_release'

as linux/swap.h doesn't include linux/pagemap.h but actually needs it
(see comments in linux/swap.h as to why this is.)

Fix that by #including &lt;linux/pagemap.h&gt; in &lt;asm/pgalloc.h&gt; as it's done
by x86.

Signed-off-by: Uwe Kleine-König &lt;u.kleine-koenig@pengutronix.de&gt;
Acked-by: Tony Lindgren &lt;tony@atomide.com&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: tlb: move noMMU tlb_flush() to asm/tlb.h</title>
<updated>2011-02-21T19:29:28+00:00</updated>
<author>
<name>Russell King</name>
<email>rmk+kernel@arm.linux.org.uk</email>
</author>
<published>2011-02-20T12:27:49+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=58e9c47fa0dd76693b2c85c010c7430a4de77c6d'/>
<id>58e9c47fa0dd76693b2c85c010c7430a4de77c6d</id>
<content type='text'>
There's no need to noMMU to put tlb_flush() in asm/tlbflush.h - it's
part of the tlb shootdown interface.  Move it to asm/tlb.h instead, as
per x86.

Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
There's no need to noMMU to put tlb_flush() in asm/tlbflush.h - it's
part of the tlb shootdown interface.  Move it to asm/tlb.h instead, as
per x86.

Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: tlb: delay page freeing for SMP and ARMv7 CPUs</title>
<updated>2011-02-21T19:29:28+00:00</updated>
<author>
<name>Russell King</name>
<email>rmk+kernel@arm.linux.org.uk</email>
</author>
<published>2011-02-20T12:16:45+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=06824ba824b3e9f2fedb38bee79af0643198ed7f'/>
<id>06824ba824b3e9f2fedb38bee79af0643198ed7f</id>
<content type='text'>
We need to delay freeing any mapped page on SMP and ARMv7 systems to
ensure that the data is not accessed by other CPUs, or is used for
speculative prefetch with ARMv7.  This includes not only mapped pages
but also pages used for the page tables themselves.

This avoids races with the MMU/other CPUs accessing pages after they've
been freed but before we've invalidated the TLB.

Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
We need to delay freeing any mapped page on SMP and ARMv7 systems to
ensure that the data is not accessed by other CPUs, or is used for
speculative prefetch with ARMv7.  This includes not only mapped pages
but also pages used for the page tables themselves.

This avoids races with the MMU/other CPUs accessing pages after they've
been freed but before we've invalidated the TLB.

Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: 6722/1: SPEAr: sp810: switch to slow mode before reset</title>
<updated>2011-02-21T19:29:24+00:00</updated>
<author>
<name>Shiraz Hashim</name>
<email>shiraz.hashim@st.com</email>
</author>
<published>2011-02-16T06:40:29+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=b8272a61c16decd4c8627fc1181bdd174c922c3f'/>
<id>b8272a61c16decd4c8627fc1181bdd174c922c3f</id>
<content type='text'>
In sysctl_soft_reset(), switch to slow mode before resetting the system
via the system controller.  This is required.

Reviewed-by: Stanley Miao &lt;stanley.miao@windriver.com&gt;
Signed-off-by: Shiraz Hashim &lt;shiraz.hashim@st.com&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
In sysctl_soft_reset(), switch to slow mode before resetting the system
via the system controller.  This is required.

Reviewed-by: Stanley Miao &lt;stanley.miao@windriver.com&gt;
Signed-off-by: Shiraz Hashim &lt;shiraz.hashim@st.com&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: 6741/1: errata: pl310 cache sync operation may be faulty</title>
<updated>2011-02-19T11:23:21+00:00</updated>
<author>
<name>Srinidhi Kasagar</name>
<email>srinidhi.kasagar@stericsson.com</email>
</author>
<published>2011-02-17T06:03:51+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=885028e4ba4caf49d565c96481e1a05220ecb517'/>
<id>885028e4ba4caf49d565c96481e1a05220ecb517</id>
<content type='text'>
The effect of cache sync operation is to drain the store buffer and
wait for all internal buffers to be empty. In normal conditions, store
buffer is able to merge the normal memory writes within its 32-byte
data buffers.  Due to this erratum present in r3p0, the effect of cache
sync operation on the store buffer still remains when the operation
completes. This means that the store buffer is always asked to drain
and this prevents it from merging any further writes.

This can severely affect performance on the write traffic esp. on
Normal memory NC one.

The proposed workaround is to replace the normal offset of cache sync
operation(0x730) by another offset targeting an unmapped PL310
register 0x740.

Signed-off-by: srinidhi kasagar &lt;srinidhi.kasagar@stericsson.com&gt;
Acked-by: Linus Walleij &lt;linus.walleij@stericsson.com&gt;
Acked-by: Catalin Marinas &lt;catalin.marinas@arm.com&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The effect of cache sync operation is to drain the store buffer and
wait for all internal buffers to be empty. In normal conditions, store
buffer is able to merge the normal memory writes within its 32-byte
data buffers.  Due to this erratum present in r3p0, the effect of cache
sync operation on the store buffer still remains when the operation
completes. This means that the store buffer is always asked to drain
and this prevents it from merging any further writes.

This can severely affect performance on the write traffic esp. on
Normal memory NC one.

The proposed workaround is to replace the normal offset of cache sync
operation(0x730) by another offset targeting an unmapped PL310
register 0x740.

Signed-off-by: srinidhi kasagar &lt;srinidhi.kasagar@stericsson.com&gt;
Acked-by: Linus Walleij &lt;linus.walleij@stericsson.com&gt;
Acked-by: Catalin Marinas &lt;catalin.marinas@arm.com&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: io: ensure inb/outb() et.al. are properly ordered on ARMv6+</title>
<updated>2011-01-31T10:53:42+00:00</updated>
<author>
<name>Russell King</name>
<email>rmk+kernel@arm.linux.org.uk</email>
</author>
<published>2011-01-30T11:29:40+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=c1928022ef94662a88329e35fa0968b1be328b8e'/>
<id>c1928022ef94662a88329e35fa0968b1be328b8e</id>
<content type='text'>
Ensure that the ISA/PCI IO space accessors are properly ordered on
ARMv6+ architectures.  These should always be ordered with respect to
all other accesses.

This also fixes __iormb() and __iowmb() not being visible to ioread/
iowrite if a platform defines its own MMIO accessors.

Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Ensure that the ISA/PCI IO space accessors are properly ordered on
ARMv6+ architectures.  These should always be ordered with respect to
all other accesses.

This also fixes __iormb() and __iowmb() not being visible to ioread/
iowrite if a platform defines its own MMIO accessors.

Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: 6637/1: Make the argument to virt_to_phys() "const volatile"</title>
<updated>2011-01-25T21:18:03+00:00</updated>
<author>
<name>Catalin Marinas</name>
<email>catalin.marinas@arm.com</email>
</author>
<published>2011-01-25T10:18:25+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=05b112ff98070dc1f3293e8cd8e4c6f468d1084a'/>
<id>05b112ff98070dc1f3293e8cd8e4c6f468d1084a</id>
<content type='text'>
Changing the virt_to_phys() argument to "const volatile void *" avoids
compiler warnings in some situations where this function is used.

Signed-off-by: Catalin Marinas &lt;catalin.marinas@arm.com&gt;
Acked-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
Acked-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Changing the virt_to_phys() argument to "const volatile void *" avoids
compiler warnings in some situations where this function is used.

Signed-off-by: Catalin Marinas &lt;catalin.marinas@arm.com&gt;
Acked-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
Acked-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: 6635/2: Configure reference clock for Versatile Express timers</title>
<updated>2011-01-25T16:18:33+00:00</updated>
<author>
<name>Pawel Moll</name>
<email>pawel.moll@arm.com</email>
</author>
<published>2011-01-25T14:53:03+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=baaece224570a935210a59257b5d9073e99843ea'/>
<id>baaece224570a935210a59257b5d9073e99843ea</id>
<content type='text'>
Timers on Versatile Express mainboard are used as system clock/event
sources. Driver assumes that they are clocked with 1MHz signal.
Old V2M firmware apparently configured it by default, but on newer
boards one can observe that "sleep 1" command takes over 30 seconds
to finish, as the timers are fed with 32kHz instead...

This patch performs required magic and also removes code clearing
timer's control registers, as exactly the same operations are
performed by the timer driver few jiffies later.

Signed-off-by: Pawel Moll &lt;pawel.moll@arm.com&gt;
Tested-by: Will Deacon &lt;will.deacon@arm.com&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Timers on Versatile Express mainboard are used as system clock/event
sources. Driver assumes that they are clocked with 1MHz signal.
Old V2M firmware apparently configured it by default, but on newer
boards one can observe that "sleep 1" command takes over 30 seconds
to finish, as the timers are fed with 32kHz instead...

This patch performs required magic and also removes code clearing
timer's control registers, as exactly the same operations are
performed by the timer driver few jiffies later.

Signed-off-by: Pawel Moll &lt;pawel.moll@arm.com&gt;
Tested-by: Will Deacon &lt;will.deacon@arm.com&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge branch 'fixes' of master.kernel.org:/home/rmk/linux-2.6-arm</title>
<updated>2011-01-15T20:29:50+00:00</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2011-01-15T20:29:50+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=65e5d002b5ad220db2bf9557f53de5a98f7dab86'/>
<id>65e5d002b5ad220db2bf9557f53de5a98f7dab86</id>
<content type='text'>
* 'fixes' of master.kernel.org:/home/rmk/linux-2.6-arm:
  ARM: fix missing branch in __error_a
  ARM: fix /proc/$PID/stack on SMP
  ARM: Fix build regression on SA11x0, PXA, and H720x targets
  ARM: 6625/1: use memblock memory regions for "System RAM" I/O resources
  ARM: fix wrongly patched constants
  ARM: 6624/1: fix dependency for CONFIG_SMP_ON_UP
  ARM: 6623/1: Thumb-2: Fix out-of-range offset for Thumb-2 in proc-v7.S
  ARM: 6622/1: fix dma_unmap_sg() documentation
  ARM: 6621/1: bitops: remove condition code clobber for CLZ
  ARM: 6620/1: Change misleading warning when CONFIG_CMDLINE_FORCE is used
  ARM: 6619/1: nommu: avoid mapping vectors page when !CONFIG_MMU
  ARM: sched_clock: make minsec argument to clocks_calc_mult_shift() zero
  ARM: sched_clock: allow init_sched_clock() to be called early
  ARM: integrator: fix compile warning in cpu.c
  ARM: 6616/1: Fix ep93xx-fb init/exit annotations
  ARM: twd: fix display of twd frequency
  ARM: udelay: prevent math rounding resulting in short udelays
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
* 'fixes' of master.kernel.org:/home/rmk/linux-2.6-arm:
  ARM: fix missing branch in __error_a
  ARM: fix /proc/$PID/stack on SMP
  ARM: Fix build regression on SA11x0, PXA, and H720x targets
  ARM: 6625/1: use memblock memory regions for "System RAM" I/O resources
  ARM: fix wrongly patched constants
  ARM: 6624/1: fix dependency for CONFIG_SMP_ON_UP
  ARM: 6623/1: Thumb-2: Fix out-of-range offset for Thumb-2 in proc-v7.S
  ARM: 6622/1: fix dma_unmap_sg() documentation
  ARM: 6621/1: bitops: remove condition code clobber for CLZ
  ARM: 6620/1: Change misleading warning when CONFIG_CMDLINE_FORCE is used
  ARM: 6619/1: nommu: avoid mapping vectors page when !CONFIG_MMU
  ARM: sched_clock: make minsec argument to clocks_calc_mult_shift() zero
  ARM: sched_clock: allow init_sched_clock() to be called early
  ARM: integrator: fix compile warning in cpu.c
  ARM: 6616/1: Fix ep93xx-fb init/exit annotations
  ARM: twd: fix display of twd frequency
  ARM: udelay: prevent math rounding resulting in short udelays
</pre>
</div>
</content>
</entry>
</feed>
