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<title>linux-stable.git/arch/arm/common, branch v3.8</title>
<subtitle>Linux kernel stable tree</subtitle>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/'/>
<entry>
<title>ARM: GIC: fix GIC cpumask initialization</title>
<updated>2013-02-08T10:17:22+00:00</updated>
<author>
<name>Russell King</name>
<email>rmk+kernel@arm.linux.org.uk</email>
</author>
<published>2013-01-30T23:49:57+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=2bb3135166abcd59979cfcdd3696ba840b6b9d45'/>
<id>2bb3135166abcd59979cfcdd3696ba840b6b9d45</id>
<content type='text'>
Punit Agrawal reports:
&gt; I was trying to boot 3.8-rc5 on Realview EB 11MPCore using
&gt; realview-smp_defconfig as a starting point but the kernel failed to
&gt; progress past the log below (config attached).
&gt;
&gt; Pawel suggested I try reverting 384a290283f - "ARM: gic: use a private
&gt; mapping for CPU target interfaces" that you've authored. With this
&gt; commit reverted the kernel boots.
&gt;
&gt; I am not quite sure why the commit breaks 11MPCore but Pawel (cc'd)
&gt; might be able to shed light on that.

Some early GIC implementations return zero for the first distributor
CPU routing register.  This means we can't rely on that telling us
which CPU interface we're connected to.  We know that these platforms
implement PPIs for IRQs 29-31 - but we shouldn't assume that these
will always be populated.

So, instead, scan for a non-zero CPU routing register in the first
32 IRQs and use that as our CPU mask.

Reported-by: Punit Agrawal &lt;punit.agrawal@arm.com&gt;
Reviewed-by: Nicolas Pitre &lt;nico@linaro.org&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
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<pre>
Punit Agrawal reports:
&gt; I was trying to boot 3.8-rc5 on Realview EB 11MPCore using
&gt; realview-smp_defconfig as a starting point but the kernel failed to
&gt; progress past the log below (config attached).
&gt;
&gt; Pawel suggested I try reverting 384a290283f - "ARM: gic: use a private
&gt; mapping for CPU target interfaces" that you've authored. With this
&gt; commit reverted the kernel boots.
&gt;
&gt; I am not quite sure why the commit breaks 11MPCore but Pawel (cc'd)
&gt; might be able to shed light on that.

Some early GIC implementations return zero for the first distributor
CPU routing register.  This means we can't rely on that telling us
which CPU interface we're connected to.  We know that these platforms
implement PPIs for IRQs 29-31 - but we shouldn't assume that these
will always be populated.

So, instead, scan for a non-zero CPU routing register in the first
32 IRQs and use that as our CPU mask.

Reported-by: Punit Agrawal &lt;punit.agrawal@arm.com&gt;
Reviewed-by: Nicolas Pitre &lt;nico@linaro.org&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge branch 'fixes' of git://git.linaro.org/people/rmk/linux-arm</title>
<updated>2013-01-09T16:58:57+00:00</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2013-01-09T16:58:57+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=5c49985c21bba4d2f899e3a97121868a5c58a876'/>
<id>5c49985c21bba4d2f899e3a97121868a5c58a876</id>
<content type='text'>
Pull ARM fixes from Russell King.

* 'fixes' of git://git.linaro.org/people/rmk/linux-arm:
  ARM: 7616/1: cache-l2x0: aurora: Use writel_relaxed instead of writel
  ARM: 7615/1: cache-l2x0: aurora: Invalidate during clean operation with WT enable
  ARM: 7614/1: mm: fix wrong branch from Cortex-A9 to PJ4b
  ARM: 7612/1: imx: Do not select some errata that depends on !ARCH_MULTIPLATFORM
  ARM: 7611/1: VIC: fix bug in VIC irqdomain code
  ARM: 7610/1: versatile: bump IRQ numbers
  ARM: 7609/1: disable errata work-arounds which access secure registers
  ARM: 7608/1: l2x0: Only set .set_debug on PL310 r3p0 and earlier
</content>
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<pre>
Pull ARM fixes from Russell King.

* 'fixes' of git://git.linaro.org/people/rmk/linux-arm:
  ARM: 7616/1: cache-l2x0: aurora: Use writel_relaxed instead of writel
  ARM: 7615/1: cache-l2x0: aurora: Invalidate during clean operation with WT enable
  ARM: 7614/1: mm: fix wrong branch from Cortex-A9 to PJ4b
  ARM: 7612/1: imx: Do not select some errata that depends on !ARCH_MULTIPLATFORM
  ARM: 7611/1: VIC: fix bug in VIC irqdomain code
  ARM: 7610/1: versatile: bump IRQ numbers
  ARM: 7609/1: disable errata work-arounds which access secure registers
  ARM: 7608/1: l2x0: Only set .set_debug on PL310 r3p0 and earlier
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: drivers: remove __dev* attributes.</title>
<updated>2013-01-03T23:57:04+00:00</updated>
<author>
<name>Greg Kroah-Hartman</name>
<email>gregkh@linuxfoundation.org</email>
</author>
<published>2012-12-21T22:02:24+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=351a102dbf489d0e9c9b0883f76e2a94d895503d'/>
<id>351a102dbf489d0e9c9b0883f76e2a94d895503d</id>
<content type='text'>
CONFIG_HOTPLUG is going away as an option.  As a result, the __dev*
markings need to be removed.

This change removes the use of __devinit, __devexit_p, __devinitdata,
and __devexit from these drivers.

Based on patches originally written by Bill Pemberton, but redone by me
in order to handle some of the coding style issues better, by hand.

Cc: Bill Pemberton &lt;wfp5p@virginia.edu&gt;
Cc: Russell King &lt;linux@arm.linux.org.uk&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
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<pre>
CONFIG_HOTPLUG is going away as an option.  As a result, the __dev*
markings need to be removed.

This change removes the use of __devinit, __devexit_p, __devinitdata,
and __devexit from these drivers.

Based on patches originally written by Bill Pemberton, but redone by me
in order to handle some of the coding style issues better, by hand.

Cc: Bill Pemberton &lt;wfp5p@virginia.edu&gt;
Cc: Russell King &lt;linux@arm.linux.org.uk&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: 7611/1: VIC: fix bug in VIC irqdomain code</title>
<updated>2013-01-02T10:35:07+00:00</updated>
<author>
<name>Linus Walleij</name>
<email>linus.walleij@linaro.org</email>
</author>
<published>2012-12-26T00:39:16+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=5ced33bc06e7e76cb8a236f15bff49eb6155b618'/>
<id>5ced33bc06e7e76cb8a236f15bff49eb6155b618</id>
<content type='text'>
The VIC irqdomain code added in commit
07c9249f1fa90cc8189bed44c0bcece664596a72
"ARM: 7554/1: VIC: use irq_domain_add_simple()"

Had two bugs:

1) It didn't call irq_create_mapping() once on each
   valid irq source in the slowpath when registering
   the controller.

2) It passed a -1 as IRQ offset for the DT case, whereas
   0 should be passed as invalid IRQ instead.

Cc: Grant Likely &lt;grant.likely@secretlab.ca&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The VIC irqdomain code added in commit
07c9249f1fa90cc8189bed44c0bcece664596a72
"ARM: 7554/1: VIC: use irq_domain_add_simple()"

Had two bugs:

1) It didn't call irq_create_mapping() once on each
   valid irq source in the slowpath when registering
   the controller.

2) It passed a -1 as IRQ offset for the DT case, whereas
   0 should be passed as invalid IRQ instead.

Cc: Grant Likely &lt;grant.likely@secretlab.ca&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge branch 'devel-stable' into for-linus</title>
<updated>2012-12-11T10:01:53+00:00</updated>
<author>
<name>Russell King</name>
<email>rmk+kernel@arm.linux.org.uk</email>
</author>
<published>2012-12-11T10:01:53+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=0fa5d3996dbda1ee9653c43d39b7ef159fb57ee7'/>
<id>0fa5d3996dbda1ee9653c43d39b7ef159fb57ee7</id>
<content type='text'>
</content>
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<pre>
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge branches 'cache-l2x0', 'fixes', 'hdrs', 'misc', 'mmci', 'vic' and 'warnings' into for-next</title>
<updated>2012-12-11T00:20:18+00:00</updated>
<author>
<name>Russell King</name>
<email>rmk+kernel@arm.linux.org.uk</email>
</author>
<published>2012-12-11T00:20:18+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=0b99cb73105f0527c1c4096960796b8772343a39'/>
<id>0b99cb73105f0527c1c4096960796b8772343a39</id>
<content type='text'>
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: 7586/1: sp804: set cpumask to cpu_possible_mask for clock event device</title>
<updated>2012-11-28T09:46:57+00:00</updated>
<author>
<name>Will Deacon</name>
<email>will.deacon@arm.com</email>
</author>
<published>2012-11-23T17:55:30+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=ea3aacf5f22c1002cac97985354658072232e280'/>
<id>ea3aacf5f22c1002cac97985354658072232e280</id>
<content type='text'>
The SP804 driver statically initialises the cpumask of the clock event
device to be cpu_all_mask, which is derived from the compile-time
constant NR_CPUS. This breaks SMP_ON_UP systems where the interrupt
controller handling the sp804 doesn't have the irq_set_affinity callback
on the irq_chip, because the common timer code fails to identify the
device as cpu-local and ends up treating it as a broadcast device
instead.

This patch fixes the problem by using cpu_possible_mask at runtime,
which will correctly represent the possible CPUs when SMP_ON_UP is being
used.

Signed-off-by: Will Deacon &lt;will.deacon@arm.com&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The SP804 driver statically initialises the cpumask of the clock event
device to be cpu_all_mask, which is derived from the compile-time
constant NR_CPUS. This breaks SMP_ON_UP systems where the interrupt
controller handling the sp804 doesn't have the irq_set_affinity callback
on the irq_chip, because the common timer code fails to identify the
device as cpu-local and ends up treating it as a broadcast device
instead.

This patch fixes the problem by using cpu_possible_mask at runtime,
which will correctly represent the possible CPUs when SMP_ON_UP is being
used.

Signed-off-by: Will Deacon &lt;will.deacon@arm.com&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: gic: use a private mapping for CPU target interfaces</title>
<updated>2012-11-19T15:44:34+00:00</updated>
<author>
<name>Nicolas Pitre</name>
<email>nicolas.pitre@linaro.org</email>
</author>
<published>2012-04-11T22:55:48+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=384a290283fde63ba8dc671fca5420111cdac19a'/>
<id>384a290283fde63ba8dc671fca5420111cdac19a</id>
<content type='text'>
The GIC interface numbering does not necessarily follow the logical
CPU numbering, especially for complex topologies such as multi-cluster
systems.

Fortunately we can easily probe the GIC to create a mapping as the
Interrupt Processor Targets Registers for the first 32 interrupts are
read-only, and each field returns a value that always corresponds to
the processor reading the register.

Initially all mappings target all CPUs in case an IPI is required to
boot secondary CPUs.  It is refined as those CPUs discover what their
actual mapping is.

Signed-off-by: Nicolas Pitre &lt;nico@linaro.org&gt;
Acked-by: Will Deacon &lt;will.deacon@arm.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The GIC interface numbering does not necessarily follow the logical
CPU numbering, especially for complex topologies such as multi-cluster
systems.

Fortunately we can easily probe the GIC to create a mapping as the
Interrupt Processor Targets Registers for the first 32 interrupts are
read-only, and each field returns a value that always corresponds to
the processor reading the register.

Initially all mappings target all CPUs in case an IPI is required to
boot secondary CPUs.  It is refined as those CPUs discover what their
actual mapping is.

Signed-off-by: Nicolas Pitre &lt;nico@linaro.org&gt;
Acked-by: Will Deacon &lt;will.deacon@arm.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: vic: fix build warning caused by previous commit</title>
<updated>2012-11-08T10:48:30+00:00</updated>
<author>
<name>Russell King</name>
<email>rmk+kernel@arm.linux.org.uk</email>
</author>
<published>2012-11-08T10:48:30+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=946c59a08a2497303750c0fee4367ca32009155c'/>
<id>946c59a08a2497303750c0fee4367ca32009155c</id>
<content type='text'>
07c9249f1f (ARM: 7554/1: VIC: use irq_domain_add_simple()) removed the
use of 'irq_base' but did not remove the variable itself, which causes:

arch/arm/common/vic.c: In function 'vic_of_init':
arch/arm/common/vic.c:410:6: warning: unused variable 'irq_base'

Remove this now unused variable.

Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
07c9249f1f (ARM: 7554/1: VIC: use irq_domain_add_simple()) removed the
use of 'irq_base' but did not remove the variable itself, which causes:

arch/arm/common/vic.c: In function 'vic_of_init':
arch/arm/common/vic.c:410:6: warning: unused variable 'irq_base'

Remove this now unused variable.

Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: 7554/1: VIC: use irq_domain_add_simple()</title>
<updated>2012-10-18T10:11:16+00:00</updated>
<author>
<name>Linus Walleij</name>
<email>linus.walleij@linaro.org</email>
</author>
<published>2012-10-16T17:50:00+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=07c9249f1fa90cc8189bed44c0bcece664596a72'/>
<id>07c9249f1fa90cc8189bed44c0bcece664596a72</id>
<content type='text'>
Instead of allocating descriptors on-the-fly for the device tree
initialization case, use irq_domain_add_simple() which will take
care of this if you pass negative as the first_irq.

Alter the signature of __vic_init() to pass the first_irq as
signed so this works as expected.

Switching the VIC to use irq_domain_add_simple() also has the
upside of displaying the same WARNING when you boot with
pre-allocated descriptors on systems using SPARSE_IRQ but
yet not using device tree.

Cc: Grant Likely &lt;grant.likely@secretlab.ca&gt;
Acked-by: Rob Herring &lt;rob.herring@calxeda.com&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Instead of allocating descriptors on-the-fly for the device tree
initialization case, use irq_domain_add_simple() which will take
care of this if you pass negative as the first_irq.

Alter the signature of __vic_init() to pass the first_irq as
signed so this works as expected.

Switching the VIC to use irq_domain_add_simple() also has the
upside of displaying the same WARNING when you boot with
pre-allocated descriptors on systems using SPARSE_IRQ but
yet not using device tree.

Cc: Grant Likely &lt;grant.likely@secretlab.ca&gt;
Acked-by: Rob Herring &lt;rob.herring@calxeda.com&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</pre>
</div>
</content>
</entry>
</feed>
