linux-stable.git/arch/arc/kernel/setup.c, branch v4.19.78

ARC: enable uboot support unconditionally

2019-08-06T17:06:57+00:00

commit 493a2f812446e92bcb1e69a77381b4d39808d730 upstream.

After reworking U-boot args handling code and adding paranoid
arguments check we can eliminate CONFIG_ARC_UBOOT_SUPPORT and
enable uboot support unconditionally.

For JTAG case we can assume that core registers will come up
reset value of 0 or in worst case we rely on user passing
'-on=clear_regs' to Metaware debugger.

Cc: stable@vger.kernel.org
Tested-by: Corentin LABBE 
Signed-off-by: Eugeniy Paltsev 
Signed-off-by: Vineet Gupta 
Signed-off-by: Greg Kroah-Hartman

ARC: u-boot args: check that magic number is correct

2019-04-20T07:15:54+00:00

[ Upstream commit edb64bca50cd736c6894cc6081d5263c007ce005 ]

In case of devboards we really often disable bootloader and load
Linux image in memory via JTAG. Even if kernel tries to verify
uboot_tag and uboot_arg there is sill a chance that we treat some
garbage in registers as valid u-boot arguments in JTAG case.
E.g. it is enough to have '1' in r0 to treat any value in r2 as
a boot command line.

So check that magic number passed from u-boot is correct and drop
u-boot arguments otherwise. That helps to reduce the possibility
of using garbage as u-boot arguments in JTAG case.

We can safely check U-boot magic value (0x0) in linux passed via
r1 register as U-boot pass it from the beginning. So there is no
backward-compatibility issues.

Signed-off-by: Eugeniy Paltsev 
Signed-off-by: Vineet Gupta 
Signed-off-by: Sasha Levin

ARCv2: don't assume core 0x54 has dual issue

2019-03-23T19:09:51+00:00

[ Upstream commit 7b2e932f633bcb7b190fc7031ce6dac75f8c3472 ]

The first release of core4 (0x54) was dual issue only (HS4x).
Newer releases allow hardware to be configured as single issue (HS3x)
or dual issue.

Prevent accessing a HS4x only aux register in HS3x, which otherwise
leads to illegal instruction exceptions

Signed-off-by: Vineet Gupta 
Signed-off-by: Sasha Levin

ARC: U-boot: check arguments paranoidly

2019-02-27T09:09:00+00:00

commit a66f2e57bd566240d8b3884eedf503928fbbe557 upstream.

Handle U-boot arguments paranoidly:
 * don't allow to pass unknown tag.
 * try to use external device tree blob only if corresponding tag
   (TAG_DTB) is set.
 * don't check uboot_tag if kernel build with no ARC_UBOOT_SUPPORT.

NOTE:
If U-boot args are invalid we skip them and try to use embedded device
tree blob. We can't panic on invalid U-boot args as we really pass
invalid args due to bug in U-boot code.
This happens if we don't provide external DTB to U-boot and
don't set 'bootargs' U-boot environment variable (which is default
case at least for HSDK board) In that case we will pass
{r0 = 1 (bootargs in r2); r1 = 0; r2 = 0;} to linux which is invalid.

While I'm at it refactor U-boot arguments handling code.

Cc: stable@vger.kernel.org
Tested-by: Corentin LABBE 
Signed-off-by: Eugeniy Paltsev 
Signed-off-by: Vineet Gupta 
Signed-off-by: Greg Kroah-Hartman

ARCv2: boot log: fix HS48 release number

2018-02-28T18:45:30+00:00

Signed-off-by: Vineet Gupta

ARC: boot log: Fix trailing semicolon

2018-01-23T19:12:28+00:00

The trailing semicolon is an empty statement that does no operation.
Removing it since it doesn't do anything.

Signed-off-by: Luis de Bethencourt 
Signed-off-by: Vineet Gupta

ARC: Fix detection of dual-issue enabled

2017-11-29T02:12:07+00:00

As per PRM bit #0 ("D") in EXEC_CTRL enables dual-issue if set to 0,
otherwise if set to 1 all instructions are executed one at a time,
i.e. dual-issue is disabled.

Signed-off-by: Alexey Brodkin 
Signed-off-by: Vineet Gupta

ARCv2: boot log: updates for HS48: dual-issue, ECC, Loop Buffer

2017-11-13T22:37:39+00:00

Print the hardware support for ECC, Loop Buffer as well as the runtime
enabled status

Note that unlike the existing boot printing, this one is not read from
pre-decoded hardware capabilty info cached in cpuinfo[] struct.
Instead we read the AUX regs on the spot and print it, without botherign
to save anywhere.

There is no point in saving static hardware capabilites in memory when
its use is very sporadic and non-performance critical, mainly for
/proc/cpuinfo. This gets worse in SMP, given it is per-cpu, and pretty
much exactly same across all cpus. So only info needed at runtime
(e.g. TLB geometry) needs to be cached in cpuinfo[]. So going fwd
we will start converting code to this paradigm.

Signed-off-by: Vineet Gupta

ARCv2: boot log: identify HS48 cores (dual issue)

2017-10-04T03:36:49+00:00

Signed-off-by: Vineet Gupta

ARC: boot log: decontaminate ARCv2 ISA_CONFIG register

2017-10-04T03:36:49+00:00

ARCv2 ISA_CONFIG and ARC700_BUILD build config registers are not
compatible. cpuinfo_arc had isa info placeholder which was mashup of bits
form both.

Untangle this by defining it off of ARCv2 ISA info and it is fine even
for ARC700 since former is a super set of latter (ARC700 buildonly has 2
bits for atomics and stack check).

At runtime, we treat ARCv2 ISA info as a generic placeholder but
populate it correctly depending on ARC700 or HS.

This paves way for adding more HS specific bits in isa info which was
colliding with the extra bits for arc700.

Signed-off-by: Vineet Gupta