linux-stable.git/arch/arc/include/asm/pgtable.h, branch v4.6.2

ARC: Fix PAE40 boot failures due to PTE truncation

2016-05-05T11:05:45+00:00

So a benign looking cleanup which macro'ized PAGE_SHIFT shifts turned
out to be bad (since it was done non-sensically across the board).

It caused boot failures with PAE40 as forced cast to (unsigned long)
from newly introduced virt_to_pfn() was causing truncatiion of the
(long long) pte/paddr values.

It is OK to use this in accessors dealing with kernel virtual address,
pointers etc, but not for PTE values themelves.

Fixes: cJ2ff5cf2735c ("ARC: mm: Use virt_to_pfn() for addr >> PAGE_SHIFT pattern)
Signed-off-by: Vineet Gupta

ARC: mm: Use virt_to_pfn() for addr >> PAGE_SHIFT pattern

2016-03-12T06:29:47+00:00

Signed-off-by: Vineet Gupta

ARC: Fix misspellings in comments.

2016-03-11T09:29:53+00:00

Signed-off-by: Adam Buchbinder 
Signed-off-by: Vineet Gupta

ARC: mm: Introduce explicit super page size support

2016-02-12T06:40:25+00:00

MMUv4 supports 2 concurrent page sizes: Normal and Super [4K to 16M]

So far Linux supported a single super page size for a given Normal page,
depending on the software page walking address split.
e.g. we had 11:8:13 address split for 8K page, which meant super page
was 2 ^(8+13) = 2M (given that THP size has to be PMD_SHIFT)

Now we turn this around, by allowing multiple Super Pages in Kconfig
(currently 2M and 16M only) and forcing page walker address split to
PGDIR_SHIFT and PAGE_SHIFT

For configs without Super page, things are same as before and
PGDIR_SHIFT can be hacked to get non default address split

The motivation for this change is a customer who needs 16M super page
and a 8K Normal page combo.

Signed-off-by: Vineet Gupta

ARC: mm: PAE40 support

2015-10-29T13:11:30+00:00

This is the first working implementation of 40-bit physical address
extension on ARCv2.

Signed-off-by: Alexey Brodkin 
Signed-off-by: Vineet Gupta

ARC: mm: preps ahead of HIGHMEM support

2015-10-28T14:01:05+00:00

Before we plug in highmem support, some of code needs to be ready for it
 - copy_user_highpage() needs to be using the kmap_atomic API
 - mk_pte() can't assume page_address()
 - do_page_fault() can't assume VMALLOC_END is end of kernel vaddr space

Signed-off-by: Alexey Brodkin 
Signed-off-by: Vineet Gupta

ARC: mm: use generic macros _BITUL()/_AC()

2015-10-28T14:01:05+00:00

Signed-off-by: Alexey Brodkin 
Signed-off-by: Vineet Gupta

ARCv2: mm: THP support

2015-10-17T12:18:18+00:00

MMUv4 in HS38x cores supports Super Pages which are basis for Linux THP
support.

Normal and Super pages can co-exist (ofcourse not overlap) in TLB with a
new bit "SZ" in TLB page desciptor to distinguish between them.
Super Page size is configurable in hardware (4K to 16M), but fixed once
RTL builds.

The exact THP size a Linx configuration will support is a function of:
 - MMU page size (typical 8K, RTL fixed)
 - software page walker address split between PGD:PTE:PFN (typical
   11:8:13, but can be changed with 1 line)

So for above default, THP size supported is 8K * 256 = 2M

Default Page Walker is 2 levels, PGD:PTE:PFN, which in THP regime
reduces to 1 level (as PTE is folded into PGD and canonically referred
to as PMD).

Thus thp PMD accessors are implemented in terms of PTE (just like sparc)

Signed-off-by: Vineet Gupta

ARC: mm: Introduce PTE_SPECIAL

2015-10-09T11:34:23+00:00

Needed for THP, but will also come in handy for fast GUP later

Signed-off-by: Vineet Gupta

ARC: mm: pte flags comsetic cleanups, comments

2015-10-09T11:34:22+00:00

No semantical changes

Signed-off-by: Vineet Gupta