linux-stable.git/Documentation/hwmon/coretemp, branch linux-3.4.y

hwmon: (coretemp) Add support for Atom CE4110/4150/4170

2014-04-14T13:44:31+00:00

commit 1102dcab849313bd5a340b299b5cf61b518fbc0f upstream.

TjMax for the CE4100 series of Atom CPUs was previously reported to be
110 degrees C.

cpuinfo logs on the web show existing CPU types CE4110, CE4150, and CE4170,
reported as "model name : Intel(R) Atom(TM) CPU CE41{1|5|7}0 @ 1.{2|6}0GHz"
with model 28 (0x1c) and stepping 10 (0x0a). Add the three known variants
to the tjmax table.

Signed-off-by: Guenter Roeck 
Acked-by: Jean Delvare 
Signed-off-by: Ben Hutchings 
Cc: Qiang Huang 
Signed-off-by: Greg Kroah-Hartman

hwmon: (coretemp) Add support for Atom D2000 and N2000 series CPU models

2014-04-14T13:44:31+00:00

commit 5592906f8b01282ea3c2acaf641fd067ad4bb3dc upstream.

Document the Atom series D2000 and N2000 (Cedar Trail) as being supported.
List and set TjMax for those series.

Cc: Fenghua Yu 
Cc: "R, Durgadoss" 
Signed-off-by: Guenter Roeck 
Signed-off-by: Jean Delvare 
Signed-off-by: Ben Hutchings 
Cc: Qiang Huang 
Signed-off-by: Greg Kroah-Hartman

hwmon: (coretemp) Improve support of recent Atom CPU models

2014-04-14T13:44:31+00:00

commit fcc14ac1a86931f38da047cf8fb634c6db7b58bc upstream.

Document the new Atom series (Tunnel Creek and Medfield) as being
supported, and list TjMax for the Atom E600 series.

Also enable the Atom tjmax heuristic for these Atom CPU models.

Signed-off-by: Jean Delvare 
Reviewed-by: Guenter Roeck 
Cc: Alexander Stein 
Cc: Fenghua Yu 
Cc: "R, Durgadoss" 
Signed-off-by: Ben Hutchings 
Cc: Qiang Huang 
Signed-off-by: Greg Kroah-Hartman

hwmon: (coretemp) Don't use threshold registers for tempX_max

2011-09-22T00:25:18+00:00

With commit c814a4c7c4aad795835583344353963a0a673eb0, the meaning of tempX_max
was changed. It no longer returns the value of bits 8:15 of
MSR_IA32_TEMPERATURE_TARGET, but instead returns the value of CPU threshold
register T1. tempX_max_hyst was added to reflect the value of temperature
threshold register T0.

As it turns out, T0 and T1 are used on some systems, presumably by the BIOS.
Also, T0 and T1 don't have a well defined meaning. The thresholds may be used
as upper or lower limits, and it is not guaranteed that T0 <= T1. Thus, the new
attribute mapping does not reflect the actual usage of the threshold registers.
Also, register contents are changed during runtime by an entity other than the
hwmon driver, meaning the values cached by the driver do not reflect actual
register contents.

Revert most of c814a4c7c4aad795835583344353963a0a673eb0 to address the problem.
Support for T0 and T1 will be added back in with a separate commit, using new
attribute names.

Signed-off-by: Guenter Roeck 
Cc: Fenghua Yu 
Cc: Durgadoss R 
Acked-by: Jean Delvare

hwmon: (coretemp) Let the user force TjMax

2011-09-22T00:25:18+00:00

On old CPUs (and even some recent Atom CPUs) TjMax can't be read from
the CPU registers, so it is guessed by the driver using a complex
heuristic which isn't reliable. So let users who know their CPU's
TjMax pass it as a module parameter.

Signed-off-by: Jean Delvare 
Cc: Fenghua Yu 
Cc: "R, Durgadoss" 
Cc: Guenter Roeck 
Cc: Alexander Stein 
Acked-by: Fenghua Yu 
Signed-off-by: Guenter Roeck

hwmon: (coretemp) Add core/pkg threshold support to Coretemp

2011-07-28T07:17:36+00:00

This patch adds the core and pkg support to coretemp.
These thresholds can be configured via the sysfs interfaces tempX_max
and tempX_max_hyst. An interrupt is generated when CPU temperature reaches
or crosses above tempX_max OR drops below tempX_max_hyst.

This patch is based on the documentation in IA Manual vol 3A, that can be
downloaded from here:
http://download.intel.com/design/processor/manuals/253668.pdf

Signed-off-by: Durgadoss R 
Signed-off-by: Guenter Roeck

hwmon: (coretemp) Merge pkgtemp with coretemp

2011-05-20T14:04:49+00:00

This patch merges the pkgtemp with coretemp driver.
The sysfs interfaces for all cores in the same pkg
are shown under one directory, in hwmon. It also
supports CONFIG_HOTPLUG_CPU. So, the sysfs interfaces
are created when each core comes online and are
removed when it goes offline.

Signed-off-by: Durgadoss R 
Cc: Fenghua Yu 
[guenter.roeck@ericsson.com: Fixed section reference errors]
Signed-off-by: Guenter Roeck

hwmon: coretemp: documentation update and cleanup

2010-08-10T03:45:10+00:00

Update coretemp supported CPU TjMax lists and some cleanup work.

Signed-off-by: Chen Gong 
Cc: Rudolf Marek 
Cc: Huaxu Wan 
Cc: Jean Delvare 
Cc: Guenter Roeck 
Signed-off-by: Andrew Morton 
Signed-off-by: Linus Torvalds

hwmon: (coretemp) Add Lynnfield CPU

2009-09-23T20:59:43+00:00

Add Lynnfield processor support. Lynnfield is a quad-core Nehalem
based microprocessor for Desktop market, which is introduced in
September 2009.

Signed-off-by: Huaxu Wan 
Signed-off-by: Kent Liu 
Acked-by: Rudolf Marek 
Signed-off-by: Jean Delvare

hwmon: (coretemp) Add support for Penryn mobile CPUs

2009-09-23T20:59:42+00:00

Following patch adds support for mobile Penryn CPUs. Intel documents this
poorly. I asked the Coretemp author for some help. This is totally untested and
may not work. Please test!

Signed-off-by: Rudolf Marek 
Cc: Huaxu Wan 
Cc: Kent Liu 
Signed-off-by: Jean Delvare