linux-stable.git/Documentation/devicetree, branch v6.18.41

dt-bindings: net: renesas,ether: Drop example "ethernet-phy-ieee802.3-c22" fallback

2026-07-24T14:16:40+00:00

[ Upstream commit 14eb1d2c03b38ce3427f299967f7a4d97ebff4c2 ]

Fix the Micrel PHY in the example which shouldn't have the
fallback "ethernet-phy-ieee802.3-c22" compatible:

Documentation/devicetree/bindings/net/renesas,ether.example.dtb: ethernet-phy@1 \
  (ethernet-phy-id0022.1537): compatible: ['ethernet-phy-id0022.1537', 'ethernet-phy-ieee802.3-c22'] is too long
        from schema $id: http://devicetree.org/schemas/net/micrel.yaml

Signed-off-by: Rob Herring (Arm) 
Reviewed-by: Andrew Lunn 
Acked-by: Conor Dooley 
Acked-by: Niklas Söderlund 
Fixes: 37a2fce09001 ("dt-bindings: sh_eth convert bindings to json-schema")
Link: https://patch.msgid.link/20260624150250.131966-2-robh@kernel.org
Signed-off-by: Jakub Kicinski 
Signed-off-by: Sasha Levin

dt-bindings: phy: sc8280xp-qmp-pcie: Disallow bifurcation register on Purwa

2026-07-24T14:16:25+00:00

[ Upstream commit b3ee497970c63cea37976aeaa84bac39611fe0eb ]

Neither of the two Gen4x4 PHYs found on Purwa supports bifurcation.
The PHY is however physically laid out as if it were to, since there
are two separate ports (A/B).

Split out a new if-then block to un-require the bifurcation register
handle to squash this warning:

purwa-iot-evk.dtb: phy@1bd4000 (qcom,x1p42100-qmp-gen4x4-pcie-phy): 'qcom,4ln-config-sel' is a required property

Fixes: 2e1ffd4c1805 ("dt-bindings: phy: qcom,qmp-pcie: Add X1P42100 PCIe Gen4x4 PHY")
Reported-by: Rob Herring 
Closes: https://lore.kernel.org/linux-arm-msm/176857775469.1631885.16133311938753588148.robh@kernel.org/
Signed-off-by: Konrad Dybcio 
Acked-by: Rob Herring (Arm) 
Link: https://patch.msgid.link/20260610-topic-purwa_phy_shutup_warning-v2-1-951c1fbfe9b2@oss.qualcomm.com
Signed-off-by: Vinod Koul 
Signed-off-by: Sasha Levin

dt-bindings: clock: qcom: Add X1P42100 camera clock controller

2026-07-24T14:16:20+00:00

[ Upstream commit 97a5e120be5d3d7cf7d221b8703921046b73f0d2 ]

Add X1P42100 camera clock controller support and clock bindings
for camera QDSS debug clocks which are applicable for both X1E80100
and X1P42100 platforms.

Reviewed-by: Krzysztof Kozlowski 
Signed-off-by: Jagadeesh Kona 
Link: https://lore.kernel.org/r/20260507-purwa-videocc-camcc-v5-2-fc3af4130282@oss.qualcomm.com
Signed-off-by: Bjorn Andersson 
Stable-dep-of: 1e6ae74ac6f2 ("clk: qcom: camcc-x1e80100: Add support for camera QDSS debug clocks")
Signed-off-by: Sasha Levin

dt-bindings: dma: nvidia,tegra186-gpc-dma: Make reset optional

2026-07-24T14:16:19+00:00

[ Upstream commit cc6049bd3fa8501ee27042df469a19ed69cf406d ]

On Tegra264, GPCDMA reset control is not exposed to Linux and is handled
by the boot firmware.

Although reset was not exposed in Tegra234 as well, the firmware supported
a dummy reset which just returns success on reset without doing an actual
reset. This is also not supported in Tegra264 BPMP. Therefore mark 'reset'
and 'reset-names' properties as required only for devices prior to
Tegra264.

This also necessitates that the Tegra264 compatible be standalone and
cannot have the fallback compatible of Tegra186. Since there is no
functional impact, we keep reset as required for Tegra234 to avoid
breaking the ABI.

Fixes: bb8c97571db5 ("dt-bindings: dma: Add Tegra264 compatible string")
Signed-off-by: Akhil R 
Acked-by: Rob Herring (Arm) 
Acked-by: Thierry Reding 
Reviewed-by: Jon Hunter 
Link: https://patch.msgid.link/20260331102303.33181-2-akhilrajeev@nvidia.com
Signed-off-by: Vinod Koul 
Signed-off-by: Sasha Levin

regulator: dt-bindings: mt6359: Drop regulator-name pattern restrictions

2026-07-24T14:15:50+00:00

[ Upstream commit cdc517688ffa2c30a64a20b558a9ecbf046c70f1 ]

The name of the regulator should match what the board design specifies
for the power rail. There should be no limitations on what the name can
be, and they definitely don't always follow the PMIC's own names.

Drop the restrictions on regulator-name.

Fixes: 8771456635d5 ("dt-bindings: regulator: Add document for MT6359 regulator")
Reviewed-by: Krzysztof Kozlowski 
Signed-off-by: Chen-Yu Tsai 
Link: https://patch.msgid.link/20260514091520.2718987-3-wenst@chromium.org
Signed-off-by: Mark Brown 
Signed-off-by: Sasha Levin

dt-bindings: vendor-prefixes: Add Displaytech Ltd.

2026-07-24T14:15:46+00:00

[ Upstream commit 42112cff8cb78ff6120983ba71bd14d52ce9dccd ]

Add "displaytech" vendor prefix for Displaytech Ltd. .

Signed-off-by: Marek Vasut 
Acked-by: Krzysztof Kozlowski 
Signed-off-by: Neil Armstrong 
Link: https://patch.msgid.link/20260422210806.80948-1-marex@nabladev.com
Signed-off-by: Sasha Levin

dt-bindings: pinctrl: nvidia,tegra234: Add missing required block

2026-07-24T14:15:44+00:00

[ Upstream commit 61b5deb5a968f7a82124f9b2591a6a151ed7273a ]

Binding should require 'reg' property, because address space cannot be
missing in the hardware and is already needed by the Linux drivers.
Require also 'compatible' by convention, although it is not strictly
necessary.

Fixes: 857982138b79 ("dt-bindings: pinctrl: Document Tegra234 pin controllers")
Signed-off-by: Krzysztof Kozlowski 
Acked-by: Rob Herring (Arm) 
Signed-off-by: Linus Walleij 
Signed-off-by: Sasha Levin

dt-bindings: timer: Remove sifive,fine-ctr-bits property

2026-07-24T14:15:43+00:00

[ Upstream commit 1ccca10755107bc8c649937d1ba69651d1ef9da2 ]

The counter width can be inferred from the compatible string, making the
explicit "sifive,fine-ctr-bits" property redundant. Remove the property
to simplify the bindings.

Fixes: 0f920690a82c ("dt-bindings: timer: Add SiFive CLINT2")
Suggested-by: Conor Dooley 
Signed-off-by: Nick Hu 
Signed-off-by: Daniel Lezcano 
Acked-by: Conor Dooley 
Link: https://lore.kernel.org/linux-riscv/20260330-relative-hardened-5ce35fe1ef57@spud/
Link: https://patch.msgid.link/20260419-clintv2-remove-fine-ctr-v1-1-7527f4d45850@sifive.com
Signed-off-by: Sasha Levin

dt-bindings: media: sun4i-a10-video-engine: Add interconnect properties

2026-07-24T14:15:41+00:00

commit 018f2dc3a42098d3b04edd1480adc51d268adb14 upstream.

The Allwinner video engine sits behind the MBUS that is represented as
an interconnect.

Make sure that the interconnect properties are valid in the binding.

Fixes: d41662e52a03 ("media: dt-bindings: media: allwinner,sun4i-a10-video-engine: Add R40 compatible")
Cc: stable@vger.kernel.org
Signed-off-by: Chen-Yu Tsai 
Acked-by: Rob Herring (Arm) 
Acked-by: Jernej Skrabec 
Signed-off-by: Nicolas Dufresne 
Signed-off-by: Hans Verkuil 
Signed-off-by: Greg Kroah-Hartman

dt-bindings: soc: bcm: Add bcm2712 compatible

2026-06-01T15:50:38+00:00

commit 34194cb385033656d347ebe45c241e4739a58125 upstream.

Add bcm2712-pm compatible and update the bindings to satisfy it's
requirements. The PM hardware block inside bcm2712 lacks the "asb"
and "rpivid_asb" register ranges and also does not have clocks, update
the bindings accordingly.

Signed-off-by: Stanimir Varbanov 
Reviewed-by: Florian Fainelli 
Acked-by: Conor Dooley 
Signed-off-by: Ulf Hansson 
Signed-off-by: Greg Kroah-Hartman