linux-stable.git/Documentation/devicetree/bindings/timer, branch v6.9 Linux kernel stable tree dt-bindings: timer: narrow regex for unit address to hex numbers 2024-04-03T13:20:33+00:00 Krzysztof Kozlowski krzysztof.kozlowski@linaro.org 2024-03-25T10:48:33+00:00 500b42091c1dd878b7a8a59ef89aba85e0054b7b Regular expression used to match the unit address part should not allow non-hex numbers. Expect at least one hex digit as well. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240325104833.33372-2-krzysztof.kozlowski@linaro.org Signed-off-by: Rob Herring <robh@kernel.org> 
Regular expression used to match the unit address part should not allow
non-hex numbers.  Expect at least one hex digit as well.

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240325104833.33372-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Rob Herring <robh@kernel.org>
Merge tag 'timers-core-2024-03-23' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 2024-03-23T21:42:45+00:00 Linus Torvalds torvalds@linux-foundation.org 2024-03-23T21:42:45+00:00 00164f477f065a0faaed7f2ca8f1c724c99b6fe1 Pull more clocksource updates from Thomas Gleixner: "A set of updates for clocksource and clockevent drivers: - A fix for the prescaler of the ARM global timer where the prescaler mask define only covered 4 bits while it is actully 8 bits wide. This obviously restricted the possible range of prescaler adjustments - A fix for the RISC-V timer which prevents a timer interrupt being raised while the timer is initialized - A set of device tree updates to support new system on chips in various drivers - Kernel-doc and other cleanups all over the place" * tag 'timers-core-2024-03-23' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: clocksource/drivers/timer-riscv: Clear timer interrupt on timer initialization dt-bindings: timer: Add support for cadence TTC PWM clocksource/drivers/arm_global_timer: Simplify prescaler register access clocksource/drivers/arm_global_timer: Guard against division by zero clocksource/drivers/arm_global_timer: Make gt_target_rate unsigned long dt-bindings: timer: add Ralink SoCs system tick counter clocksource: arm_global_timer: fix non-kernel-doc comment clocksource/drivers/arm_global_timer: Remove stray tab clocksource/drivers/arm_global_timer: Fix maximum prescaler value clocksource/drivers/imx-sysctr: Add i.MX95 support clocksource/drivers/imx-sysctr: Drop use global variables dt-bindings: timer: nxp,sysctr-timer: support i.MX95 dt-bindings: timer: renesas: ostm: Document RZ/Five SoC dt-bindings: timer: renesas,tmu: Document input capture interrupt clocksource/drivers/ti-32K: Fix misuse of "/**" comment clocksource/drivers/stm32: Fix all kernel-doc warnings dt-bindings: timer: exynos4210-mct: Add google,gs101-mct compatible clocksource/drivers/imx: Fix -Wunused-but-set-variable warning 
Pull more clocksource updates from Thomas Gleixner:
 "A set of updates for clocksource and clockevent drivers:

   - A fix for the prescaler of the ARM global timer where the prescaler
     mask define only covered 4 bits while it is actully 8 bits wide.
     This obviously restricted the possible range of prescaler
     adjustments

   - A fix for the RISC-V timer which prevents a timer interrupt being
     raised while the timer is initialized

   - A set of device tree updates to support new system on chips in
     various drivers

   - Kernel-doc and other cleanups all over the place"

* tag 'timers-core-2024-03-23' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  clocksource/drivers/timer-riscv: Clear timer interrupt on timer initialization
  dt-bindings: timer: Add support for cadence TTC PWM
  clocksource/drivers/arm_global_timer: Simplify prescaler register access
  clocksource/drivers/arm_global_timer: Guard against division by zero
  clocksource/drivers/arm_global_timer: Make gt_target_rate unsigned long
  dt-bindings: timer: add Ralink SoCs system tick counter
  clocksource: arm_global_timer: fix non-kernel-doc comment
  clocksource/drivers/arm_global_timer: Remove stray tab
  clocksource/drivers/arm_global_timer: Fix maximum prescaler value
  clocksource/drivers/imx-sysctr: Add i.MX95 support
  clocksource/drivers/imx-sysctr: Drop use global variables
  dt-bindings: timer: nxp,sysctr-timer: support i.MX95
  dt-bindings: timer: renesas: ostm: Document RZ/Five SoC
  dt-bindings: timer: renesas,tmu: Document input capture interrupt
  clocksource/drivers/ti-32K: Fix misuse of "/**" comment
  clocksource/drivers/stm32: Fix all kernel-doc warnings
  dt-bindings: timer: exynos4210-mct: Add google,gs101-mct compatible
  clocksource/drivers/imx: Fix -Wunused-but-set-variable warning
Merge tag 'timers-v6.9-rc1' of https://git.linaro.org/people/daniel.lezcano/linux into timers/core 2024-03-18T10:01:13+00:00 Thomas Gleixner tglx@linutronix.de 2024-03-18T10:01:13+00:00 86c54c846e126d6f7cbfacefa0cfeaed6f67207b Pull clocksource/event driver updates from Daniel Lezcano: - Fix -Wunused-but-set-variable warning for the iMX GPT timer (Daniel Lezcano) - Add Pixel6 compatible string for Exynos 4210 MCT timer (Peter Griffin) - Fix all kernel-doc warnings and misuse of comment format (Randy Dunlap) - Document in the DT bindings the interrupt used for input capture interrupt and udpate the example to match the reality (Geert Uytterhoeven) - Document RZ/Five SoC DT bindings (Lad Prabhakar) - Add DT bindings support for the i.MX95, reorganize the driver to move globale variables to a timer private structure and introduce the i.MX95 timer support (Peng Fan) - Fix prescalar value to conform to the ARM global timer documentation. Fix data types and comparison, guard the divide by zero code section and use the available macros for bit manipulation (Martin Blumenstingl) - Add Ralink SoCs system tick counter (Sergio Paracuellos) - Add support for cadence TTC PWM (Mubin Sayyed) - Clear timer interrupt on timer initialization to prevent the interrupt to fire during setup (Ley Foon Tan) Link: https://lore.kernel.org/r/5552010a-1ce2-46a1-a740-a69f2e9a2cf2@linaro.org 
Pull clocksource/event driver updates from Daniel Lezcano:

  - Fix -Wunused-but-set-variable warning for the iMX GPT timer (Daniel
    Lezcano)

  - Add Pixel6 compatible string for Exynos 4210 MCT timer (Peter Griffin)

  - Fix all kernel-doc warnings and misuse of comment format (Randy
    Dunlap)

  - Document in the DT bindings the interrupt used for input capture
    interrupt and udpate the example to match the reality (Geert
    Uytterhoeven)

  - Document RZ/Five SoC DT bindings (Lad Prabhakar)

  - Add DT bindings support for the i.MX95, reorganize the driver to
    move globale variables to a timer private structure and introduce
    the i.MX95 timer support (Peng Fan)

  - Fix prescalar value to conform to the ARM global timer
    documentation. Fix data types and comparison, guard the divide by
    zero code section and use the available macros for bit manipulation
    (Martin Blumenstingl)

  - Add Ralink SoCs system tick counter (Sergio Paracuellos)

  - Add support for cadence TTC PWM (Mubin Sayyed)

  - Clear timer interrupt on timer initialization to prevent the
    interrupt to fire during setup (Ley Foon Tan)

Link: https://lore.kernel.org/r/5552010a-1ce2-46a1-a740-a69f2e9a2cf2@linaro.org
dt-bindings: timer: mediatek: Convert to json-schema 2024-03-07T18:17:52+00:00 AngeloGioacchino Del Regno angelogioacchino.delregno@collabora.com 2022-09-29T12:29:01+00:00 5d3d723470996d3b9050a89427d9fc72cd0241e9 Convert the MediaTek SoC timer txt binding to json-schema. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220929122901.614315-3-angelogioacchino.delregno@collabora.com [robh: Add mt8365 compatible, drop duplicate mediatek,mt6795-systimer, drop quotes] Signed-off-by: Rob Herring <robh@kernel.org> 
Convert the MediaTek SoC timer txt binding to json-schema.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220929122901.614315-3-angelogioacchino.delregno@collabora.com
[robh: Add mt8365 compatible, drop duplicate mediatek,mt6795-systimer, drop quotes]
Signed-off-by: Rob Herring <robh@kernel.org>
dt-bindings: timer: Add support for cadence TTC PWM 2024-02-26T14:43:58+00:00 Mubin Sayyed mubin.sayyed@amd.com 2024-02-26T09:33:33+00:00 c819dbd078321f948101ef7a19f1e171164bb3cf Cadence TTC can act as PWM device, it will be supported through separate PWM framework based driver. Decision to configure specific TTC device as PWM or clocksource/clockevent would be done based on presence of "#pwm-cells" property. Also, interrupt property is not required for TTC PWM driver. Update bindings to support TTC PWM configuration. Signed-off-by: Mubin Sayyed <mubin.sayyed@amd.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/20240226093333.2581092-1-mubin.sayyed@amd.com 
Cadence TTC can act as PWM device, it will be supported through
separate PWM framework based driver. Decision to configure
specific TTC device as PWM or clocksource/clockevent would
be done based on presence of "#pwm-cells" property.

Also, interrupt property is not required for TTC PWM driver.
Update bindings to support TTC PWM configuration.

Signed-off-by: Mubin Sayyed <mubin.sayyed@amd.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/20240226093333.2581092-1-mubin.sayyed@amd.com
dt-bindings: timer: add Ralink SoCs system tick counter 2024-02-23T12:22:45+00:00 Sergio Paracuellos sergio.paracuellos@gmail.com 2023-12-12T09:34:43+00:00 ec64db6955c5ad7e8fd03f7a52f8df84f943a9b8 Add YAML doc for the system tick counter which is present on Ralink SoCs. cc: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/20231212093443.1898591-1-sergio.paracuellos@gmail.com 
Add YAML doc for the system tick counter which is present on Ralink SoCs.

cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/20231212093443.1898591-1-sergio.paracuellos@gmail.com
dt-bindings: timer: nxp,sysctr-timer: support i.MX95 2024-02-18T09:45:05+00:00 Peng Fan peng.fan@nxp.com 2024-02-05T03:17:57+00:00 8ec11bd89e15f7858359f2c4c9eed1d7de739c3c Add i.MX95 System counter module compatible string, the SCMI firmware blocks access to control register, so should not add "nxp,sysctr-timer" as fallback. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/20240205-imx-sysctr-v4-1-ca5a6e1552e7@nxp.com 
Add i.MX95 System counter module compatible string, the SCMI
firmware blocks access to control register, so should not
add "nxp,sysctr-timer" as fallback.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/20240205-imx-sysctr-v4-1-ca5a6e1552e7@nxp.com
dt-bindings: timer: renesas: ostm: Document RZ/Five SoC 2024-02-13T13:02:41+00:00 Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com 2023-11-15T21:29:08+00:00 69518264da6298fb1a490ca8adcfcb798c16e15c The OSTM block on the RZ/Five SoC is identical to one found on the RZ/G2UL SoC. "renesas,r9a07g043-ostm" compatible string will be used on the RZ/Five SoC so to make this clear and to keep this file consistent, update the comment to include RZ/Five SoC. No driver changes are required as generic compatible string "renesas,ostm" will be used as a fallback on RZ/Five SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/20231115212908.33131-1-prabhakar.mahadev-lad.rj@bp.renesas.com 
The OSTM block on the RZ/Five SoC is identical to one found on the RZ/G2UL
SoC. "renesas,r9a07g043-ostm" compatible string will be used on the RZ/Five
SoC so to make this clear and to keep this file consistent, update the
comment to include RZ/Five SoC.

No driver changes are required as generic compatible string "renesas,ostm"
will be used as a fallback on RZ/Five SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/20231115212908.33131-1-prabhakar.mahadev-lad.rj@bp.renesas.com
MAINTAINERS: Drop my "+dt" sub-address 2024-01-31T22:05:18+00:00 Rob Herring robh@kernel.org 2024-01-22T21:15:26+00:00 442fd190d3471afdfd9ac8e067bc5e2aff88213c I never really implemented any filtering on the "+dt" sub-address, so drop it. Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com> # for I2C Link: https://lore.kernel.org/r/20240122211528.1719994-1-robh@kernel.org Signed-off-by: Rob Herring <robh@kernel.org> 
I never really implemented any filtering on the "+dt" sub-address, so
drop it.

Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com> # for I2C
Link: https://lore.kernel.org/r/20240122211528.1719994-1-robh@kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
dt-bindings: timer: renesas,tmu: Document input capture interrupt 2024-01-31T21:12:18+00:00 Geert Uytterhoeven geert+renesas@glider.be 2024-01-31T16:11:45+00:00 0076a37a426b6c850a0b41b814952760e4a70fcf Some Timer Unit (TMU) instances with 3 channels support a fourth interrupt: an input capture interrupt for the third channel. While at it, document the meaning of the four interrupts, and add "interrupt-names" for clarity. Update the example to match reality. Inspired by a patch by Yoshinori Sato for SH. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/8cb38b5236213a467c6c0073f97ccc4bfd5a39ff.1706717378.git.geert+renesas@glider.be 
Some Timer Unit (TMU) instances with 3 channels support a fourth
interrupt: an input capture interrupt for the third channel.

While at it, document the meaning of the four interrupts, and add
"interrupt-names" for clarity.

Update the example to match reality.

Inspired by a patch by Yoshinori Sato for SH.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/8cb38b5236213a467c6c0073f97ccc4bfd5a39ff.1706717378.git.geert+renesas@glider.be