linux-stable.git/Documentation/devicetree/bindings/timer, branch v6.10 Linux kernel stable tree Merge tag 'devicetree-for-6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux 2024-05-18T00:27:49+00:00 Linus Torvalds torvalds@linux-foundation.org 2024-05-18T00:27:49+00:00 06f054b1fee83415fe35204845708988fc16ef22 Pull devicetree updates from Rob Herring: "DT Bindings: - Convert samsung,exynos5-dp, atmel,lcdc, aspeed,ast2400-wdt bindings to schemas - Add bindings for Allwinner H616 NMI controller, Renesas r8a779g0 irqc, Renesas R-Car V4M TMU and CMT timers, Freescale S32G3 linflexuart, and Mediatek MT7988 XHCI - Add 'reg' constraints on DSI and SPI display panels - More dropping of unnecessary quotes in schemas - Use full paths rather than relative paths in schema $refs - Drop redundant storing of phandle for reserved memory DT Core: - Use scope based cleanups for kfree() and of_node_put() - Track interrupt-map and power-supplies for fw_devlink - Add buffer overflow check in of_modalias() - Add and use __of_prop_free() helper for freeing struct property" * tag 'devicetree-for-6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (25 commits) of: property: Add fw_devlink support for interrupt-map property dt-bindings: display: panel: constrain 'reg' in DSI panels dt-bindings: display: panel: constrain 'reg' in SPI panels dt-bindings: display: samsung,ams495qa01: add missing SPI properties ref dt-bindings: Use full path to other schemas dt-bindings: PCI: qcom,pcie-sm8350: Drop redundant 'oneOf' sub-schema of: module: add buffer overflow check in of_modalias() dt-bindings: PCI: microchip: increase number of items in ranges property dt-bindings: Drop unnecessary quotes on keys dt-bindings: interrupt-controller: mediatek,mt6577-sysirq: Drop unnecessary quotes of: property: Use scope based cleanup on port_node of: reserved_mem: Remove the use of phandle from the reserved_mem APIs of: property: fw_devlink: Add support for "power-supplies" binding dt-bindings: watchdog: aspeed,ast2400-wdt: Convert to DT schema dt-bindings: irq: sun7i-nmi: Add binding for the H616 NMI controller dt-bindings: interrupt-controller: renesas,irqc: Add r8a779g0 support dt-bindings: timer: renesas,tmu: Add R-Car V4M support dt-bindings: timer: renesas,cmt: Add R-Car V4M support of: Use scope based of_node_put() cleanups of: Use scope based kfree() cleanups ... 
Pull devicetree updates from Rob Herring:
 "DT Bindings:

   - Convert samsung,exynos5-dp, atmel,lcdc, aspeed,ast2400-wdt bindings
     to schemas

   - Add bindings for Allwinner H616 NMI controller, Renesas r8a779g0
     irqc, Renesas R-Car V4M TMU and CMT timers, Freescale S32G3
     linflexuart, and Mediatek MT7988 XHCI

   - Add 'reg' constraints on DSI and SPI display panels

   - More dropping of unnecessary quotes in schemas

   - Use full paths rather than relative paths in schema $refs

   - Drop redundant storing of phandle for reserved memory

  DT Core:

   - Use scope based cleanups for kfree() and of_node_put()

   - Track interrupt-map and power-supplies for fw_devlink

   - Add buffer overflow check in of_modalias()

   - Add and use __of_prop_free() helper for freeing struct property"

* tag 'devicetree-for-6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (25 commits)
  of: property: Add fw_devlink support for interrupt-map property
  dt-bindings: display: panel: constrain 'reg' in DSI panels
  dt-bindings: display: panel: constrain 'reg' in SPI panels
  dt-bindings: display: samsung,ams495qa01: add missing SPI properties ref
  dt-bindings: Use full path to other schemas
  dt-bindings: PCI: qcom,pcie-sm8350: Drop redundant 'oneOf' sub-schema
  of: module: add buffer overflow check in of_modalias()
  dt-bindings: PCI: microchip: increase number of items in ranges property
  dt-bindings: Drop unnecessary quotes on keys
  dt-bindings: interrupt-controller: mediatek,mt6577-sysirq: Drop unnecessary quotes
  of: property: Use scope based cleanup on port_node
  of: reserved_mem: Remove the use of phandle from the reserved_mem APIs
  of: property: fw_devlink: Add support for "power-supplies" binding
  dt-bindings: watchdog: aspeed,ast2400-wdt: Convert to DT schema
  dt-bindings: irq: sun7i-nmi: Add binding for the H616 NMI controller
  dt-bindings: interrupt-controller: renesas,irqc: Add r8a779g0 support
  dt-bindings: timer: renesas,tmu: Add R-Car V4M support
  dt-bindings: timer: renesas,cmt: Add R-Car V4M support
  of: Use scope based of_node_put() cleanups
  of: Use scope based kfree() cleanups
  ...
dt-bindings: timer: renesas: ostm: Document Renesas RZ/V2H(P) SoC 2024-05-10T08:41:52+00:00 Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com 2024-03-22T15:12:18+00:00 6402eb802deb312e33c24699f68fb7775b2c7386 Document the General Timer Module (a.k.a OSTM) block on Renesas RZ/V2H(P) ("R9A09G057") SoC, which is identical to the one found on the RZ/A1H and RZ/G2L SoCs. Add the "renesas,r9a09g057-ostm" compatible string for the RZ/V2H(P) SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/20240322151219.885832-2-prabhakar.mahadev-lad.rj@bp.renesas.com 
Document the General Timer Module (a.k.a OSTM) block on Renesas RZ/V2H(P)
("R9A09G057") SoC, which is identical to the one found on the RZ/A1H and
RZ/G2L SoCs. Add the "renesas,r9a09g057-ostm" compatible string for the
RZ/V2H(P) SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/20240322151219.885832-2-prabhakar.mahadev-lad.rj@bp.renesas.com
dt-bindings: timer: renesas,tmu: Add R-Car V4M support 2024-04-16T16:06:44+00:00 Geert Uytterhoeven geert+renesas@glider.be 2024-04-02T14:37:02+00:00 58d4b25c883192377bf6255a46d46d0589e6f4ca Document support for the Timer Unit (TMU) in the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/8a39386b1a33db6e83e852b3b365bc1adeb25242.1712068574.git.geert+renesas@glider.be Signed-off-by: Rob Herring (Arm) <robh@kernel.org> 
Document support for the Timer Unit (TMU) in the Renesas R-Car V4M
(R8A779H0) SoC.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/8a39386b1a33db6e83e852b3b365bc1adeb25242.1712068574.git.geert+renesas@glider.be
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
dt-bindings: timer: renesas,cmt: Add R-Car V4M support 2024-04-16T15:31:14+00:00 Geert Uytterhoeven geert+renesas@glider.be 2024-04-02T14:36:05+00:00 ed53d391b6401d624172d1c97458d115893c6e0b Document support for the Compare Match Timer Type0 (CMT0) and Type1 (CMT1) in the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/3e8a7a93261d8ad264dec2fa2784fe1bbfc4a23c.1712068536.git.geert+renesas@glider.be Signed-off-by: Rob Herring (Arm) <robh@kernel.org> 
Document support for the Compare Match Timer Type0 (CMT0) and Type1
(CMT1) in the Renesas R-Car V4M (R8A779H0) SoC.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/3e8a7a93261d8ad264dec2fa2784fe1bbfc4a23c.1712068536.git.geert+renesas@glider.be
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
dt-bindings: timer: narrow regex for unit address to hex numbers 2024-04-03T13:20:33+00:00 Krzysztof Kozlowski krzysztof.kozlowski@linaro.org 2024-03-25T10:48:33+00:00 500b42091c1dd878b7a8a59ef89aba85e0054b7b Regular expression used to match the unit address part should not allow non-hex numbers. Expect at least one hex digit as well. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240325104833.33372-2-krzysztof.kozlowski@linaro.org Signed-off-by: Rob Herring <robh@kernel.org> 
Regular expression used to match the unit address part should not allow
non-hex numbers.  Expect at least one hex digit as well.

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240325104833.33372-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Rob Herring <robh@kernel.org>
Merge tag 'timers-core-2024-03-23' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 2024-03-23T21:42:45+00:00 Linus Torvalds torvalds@linux-foundation.org 2024-03-23T21:42:45+00:00 00164f477f065a0faaed7f2ca8f1c724c99b6fe1 Pull more clocksource updates from Thomas Gleixner: "A set of updates for clocksource and clockevent drivers: - A fix for the prescaler of the ARM global timer where the prescaler mask define only covered 4 bits while it is actully 8 bits wide. This obviously restricted the possible range of prescaler adjustments - A fix for the RISC-V timer which prevents a timer interrupt being raised while the timer is initialized - A set of device tree updates to support new system on chips in various drivers - Kernel-doc and other cleanups all over the place" * tag 'timers-core-2024-03-23' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: clocksource/drivers/timer-riscv: Clear timer interrupt on timer initialization dt-bindings: timer: Add support for cadence TTC PWM clocksource/drivers/arm_global_timer: Simplify prescaler register access clocksource/drivers/arm_global_timer: Guard against division by zero clocksource/drivers/arm_global_timer: Make gt_target_rate unsigned long dt-bindings: timer: add Ralink SoCs system tick counter clocksource: arm_global_timer: fix non-kernel-doc comment clocksource/drivers/arm_global_timer: Remove stray tab clocksource/drivers/arm_global_timer: Fix maximum prescaler value clocksource/drivers/imx-sysctr: Add i.MX95 support clocksource/drivers/imx-sysctr: Drop use global variables dt-bindings: timer: nxp,sysctr-timer: support i.MX95 dt-bindings: timer: renesas: ostm: Document RZ/Five SoC dt-bindings: timer: renesas,tmu: Document input capture interrupt clocksource/drivers/ti-32K: Fix misuse of "/**" comment clocksource/drivers/stm32: Fix all kernel-doc warnings dt-bindings: timer: exynos4210-mct: Add google,gs101-mct compatible clocksource/drivers/imx: Fix -Wunused-but-set-variable warning 
Pull more clocksource updates from Thomas Gleixner:
 "A set of updates for clocksource and clockevent drivers:

   - A fix for the prescaler of the ARM global timer where the prescaler
     mask define only covered 4 bits while it is actully 8 bits wide.
     This obviously restricted the possible range of prescaler
     adjustments

   - A fix for the RISC-V timer which prevents a timer interrupt being
     raised while the timer is initialized

   - A set of device tree updates to support new system on chips in
     various drivers

   - Kernel-doc and other cleanups all over the place"

* tag 'timers-core-2024-03-23' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  clocksource/drivers/timer-riscv: Clear timer interrupt on timer initialization
  dt-bindings: timer: Add support for cadence TTC PWM
  clocksource/drivers/arm_global_timer: Simplify prescaler register access
  clocksource/drivers/arm_global_timer: Guard against division by zero
  clocksource/drivers/arm_global_timer: Make gt_target_rate unsigned long
  dt-bindings: timer: add Ralink SoCs system tick counter
  clocksource: arm_global_timer: fix non-kernel-doc comment
  clocksource/drivers/arm_global_timer: Remove stray tab
  clocksource/drivers/arm_global_timer: Fix maximum prescaler value
  clocksource/drivers/imx-sysctr: Add i.MX95 support
  clocksource/drivers/imx-sysctr: Drop use global variables
  dt-bindings: timer: nxp,sysctr-timer: support i.MX95
  dt-bindings: timer: renesas: ostm: Document RZ/Five SoC
  dt-bindings: timer: renesas,tmu: Document input capture interrupt
  clocksource/drivers/ti-32K: Fix misuse of "/**" comment
  clocksource/drivers/stm32: Fix all kernel-doc warnings
  dt-bindings: timer: exynos4210-mct: Add google,gs101-mct compatible
  clocksource/drivers/imx: Fix -Wunused-but-set-variable warning
Merge tag 'timers-v6.9-rc1' of https://git.linaro.org/people/daniel.lezcano/linux into timers/core 2024-03-18T10:01:13+00:00 Thomas Gleixner tglx@linutronix.de 2024-03-18T10:01:13+00:00 86c54c846e126d6f7cbfacefa0cfeaed6f67207b Pull clocksource/event driver updates from Daniel Lezcano: - Fix -Wunused-but-set-variable warning for the iMX GPT timer (Daniel Lezcano) - Add Pixel6 compatible string for Exynos 4210 MCT timer (Peter Griffin) - Fix all kernel-doc warnings and misuse of comment format (Randy Dunlap) - Document in the DT bindings the interrupt used for input capture interrupt and udpate the example to match the reality (Geert Uytterhoeven) - Document RZ/Five SoC DT bindings (Lad Prabhakar) - Add DT bindings support for the i.MX95, reorganize the driver to move globale variables to a timer private structure and introduce the i.MX95 timer support (Peng Fan) - Fix prescalar value to conform to the ARM global timer documentation. Fix data types and comparison, guard the divide by zero code section and use the available macros for bit manipulation (Martin Blumenstingl) - Add Ralink SoCs system tick counter (Sergio Paracuellos) - Add support for cadence TTC PWM (Mubin Sayyed) - Clear timer interrupt on timer initialization to prevent the interrupt to fire during setup (Ley Foon Tan) Link: https://lore.kernel.org/r/5552010a-1ce2-46a1-a740-a69f2e9a2cf2@linaro.org 
Pull clocksource/event driver updates from Daniel Lezcano:

  - Fix -Wunused-but-set-variable warning for the iMX GPT timer (Daniel
    Lezcano)

  - Add Pixel6 compatible string for Exynos 4210 MCT timer (Peter Griffin)

  - Fix all kernel-doc warnings and misuse of comment format (Randy
    Dunlap)

  - Document in the DT bindings the interrupt used for input capture
    interrupt and udpate the example to match the reality (Geert
    Uytterhoeven)

  - Document RZ/Five SoC DT bindings (Lad Prabhakar)

  - Add DT bindings support for the i.MX95, reorganize the driver to
    move globale variables to a timer private structure and introduce
    the i.MX95 timer support (Peng Fan)

  - Fix prescalar value to conform to the ARM global timer
    documentation. Fix data types and comparison, guard the divide by
    zero code section and use the available macros for bit manipulation
    (Martin Blumenstingl)

  - Add Ralink SoCs system tick counter (Sergio Paracuellos)

  - Add support for cadence TTC PWM (Mubin Sayyed)

  - Clear timer interrupt on timer initialization to prevent the
    interrupt to fire during setup (Ley Foon Tan)

Link: https://lore.kernel.org/r/5552010a-1ce2-46a1-a740-a69f2e9a2cf2@linaro.org
dt-bindings: timer: mediatek: Convert to json-schema 2024-03-07T18:17:52+00:00 AngeloGioacchino Del Regno angelogioacchino.delregno@collabora.com 2022-09-29T12:29:01+00:00 5d3d723470996d3b9050a89427d9fc72cd0241e9 Convert the MediaTek SoC timer txt binding to json-schema. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220929122901.614315-3-angelogioacchino.delregno@collabora.com [robh: Add mt8365 compatible, drop duplicate mediatek,mt6795-systimer, drop quotes] Signed-off-by: Rob Herring <robh@kernel.org> 
Convert the MediaTek SoC timer txt binding to json-schema.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220929122901.614315-3-angelogioacchino.delregno@collabora.com
[robh: Add mt8365 compatible, drop duplicate mediatek,mt6795-systimer, drop quotes]
Signed-off-by: Rob Herring <robh@kernel.org>
dt-bindings: timer: Add support for cadence TTC PWM 2024-02-26T14:43:58+00:00 Mubin Sayyed mubin.sayyed@amd.com 2024-02-26T09:33:33+00:00 c819dbd078321f948101ef7a19f1e171164bb3cf Cadence TTC can act as PWM device, it will be supported through separate PWM framework based driver. Decision to configure specific TTC device as PWM or clocksource/clockevent would be done based on presence of "#pwm-cells" property. Also, interrupt property is not required for TTC PWM driver. Update bindings to support TTC PWM configuration. Signed-off-by: Mubin Sayyed <mubin.sayyed@amd.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/20240226093333.2581092-1-mubin.sayyed@amd.com 
Cadence TTC can act as PWM device, it will be supported through
separate PWM framework based driver. Decision to configure
specific TTC device as PWM or clocksource/clockevent would
be done based on presence of "#pwm-cells" property.

Also, interrupt property is not required for TTC PWM driver.
Update bindings to support TTC PWM configuration.

Signed-off-by: Mubin Sayyed <mubin.sayyed@amd.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/20240226093333.2581092-1-mubin.sayyed@amd.com
dt-bindings: timer: add Ralink SoCs system tick counter 2024-02-23T12:22:45+00:00 Sergio Paracuellos sergio.paracuellos@gmail.com 2023-12-12T09:34:43+00:00 ec64db6955c5ad7e8fd03f7a52f8df84f943a9b8 Add YAML doc for the system tick counter which is present on Ralink SoCs. cc: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/20231212093443.1898591-1-sergio.paracuellos@gmail.com 
Add YAML doc for the system tick counter which is present on Ralink SoCs.

cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/20231212093443.1898591-1-sergio.paracuellos@gmail.com