linux-stable.git/Documentation/devicetree/bindings/soc, branch linux-4.2.y Linux kernel stable tree Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc 2015-06-26T18:54:29+00:00 Linus Torvalds torvalds@linux-foundation.org 2015-06-26T18:54:29+00:00 f5dcb68086ba2e033b2af32b0da0c7a7c7872a09 Pull ARM SoC driver updates from Kevin Hilman: "Some of these are for drivers/soc, where we're now putting SoC-specific drivers these days. Some are for other driver subsystems where we have received acks from the appropriate maintainers. Some highlights: - simple-mfd: document DT bindings and misc updates - migrate mach-berlin to simple-mfd for clock, pinctrl and reset - memory: support for Tegra132 SoC - memory: introduce tegra EMC driver for scaling memory frequency - misc. updates for ARM CCI and CCN busses" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (48 commits) drivers: soc: sunxi: Introduce SoC driver to map SRAMs arm-cci: Add aliases for PMU events arm-cci: Add CCI-500 PMU support arm-cci: Sanitise CCI400 PMU driver specific code arm-cci: Abstract handling for CCI events arm-cci: Abstract out the PMU counter details arm-cci: Cleanup PMU driver code arm-cci: Do not enable CCI-400 PMU by default firmware: qcom: scm: Add HDCP Support ARM: berlin: add an ADC node for the BG2Q ARM: berlin: remove useless chip and system ctrl compatibles clk: berlin: drop direct of_iomap of nodes reg property ARM: berlin: move BG2Q clock node ARM: berlin: move BG2CD clock node ARM: berlin: move BG2 clock node clk: berlin: prepare simple-mfd conversion pinctrl: berlin: drop SoC stub provided regmap ARM: berlin: move pinctrl to simple-mfd nodes pinctrl: berlin: prepare to use regmap provided by syscon reset: berlin: drop arch_initcall initialization ... 
Pull ARM SoC driver updates from Kevin Hilman:
 "Some of these are for drivers/soc, where we're now putting
  SoC-specific drivers these days.  Some are for other driver subsystems
  where we have received acks from the appropriate maintainers.

  Some highlights:

   - simple-mfd: document DT bindings and misc updates
   - migrate mach-berlin to simple-mfd for clock, pinctrl and reset
   - memory: support for Tegra132 SoC
   - memory: introduce tegra EMC driver for scaling memory frequency
   - misc. updates for ARM CCI and CCN busses"

* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (48 commits)
  drivers: soc: sunxi: Introduce SoC driver to map SRAMs
  arm-cci: Add aliases for PMU events
  arm-cci: Add CCI-500 PMU support
  arm-cci: Sanitise CCI400 PMU driver specific code
  arm-cci: Abstract handling for CCI events
  arm-cci: Abstract out the PMU counter details
  arm-cci: Cleanup PMU driver code
  arm-cci: Do not enable CCI-400 PMU by default
  firmware: qcom: scm: Add HDCP Support
  ARM: berlin: add an ADC node for the BG2Q
  ARM: berlin: remove useless chip and system ctrl compatibles
  clk: berlin: drop direct of_iomap of nodes reg property
  ARM: berlin: move BG2Q clock node
  ARM: berlin: move BG2CD clock node
  ARM: berlin: move BG2 clock node
  clk: berlin: prepare simple-mfd conversion
  pinctrl: berlin: drop SoC stub provided regmap
  ARM: berlin: move pinctrl to simple-mfd nodes
  pinctrl: berlin: prepare to use regmap provided by syscon
  reset: berlin: drop arch_initcall initialization
  ...
powerpc/qman: Change fsl,qman-channel-id to cell-index 2015-06-03T02:37:24+00:00 Scott Wood scottwood@freescale.com 2015-04-17T22:53:06+00:00 e9326dea3fe76f38493d1b74999c45707fdc906d It turns out that existing U-Boots will dereference NULL pointers if the device tree does not have cell-index in the portal nodes. No patch has yet been merged adding device tree nodes for this binding (except a dtsi that has not yet been referenced), nor has any driver yet been merged making use of the binding, so it's not too late to change the binding in order to keep compatibility with existing U-Boots. Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Madalin-Cristian Bucur <madalin.bucur@freescale.com> 
It turns out that existing U-Boots will dereference NULL pointers
if the device tree does not have cell-index in the portal nodes.

No patch has yet been merged adding device tree nodes for this binding
(except a dtsi that has not yet been referenced), nor has any driver
yet been merged making use of the binding, so it's not too late to
change the binding in order to keep compatibility with existing
U-Boots.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Madalin-Cristian Bucur <madalin.bucur@freescale.com>
drivers: soc: sunxi: Introduce SoC driver to map SRAMs 2015-06-01T15:57:34+00:00 Maxime Ripard maxime.ripard@free-electrons.com 2015-06-01T09:04:26+00:00 4af34b572a85c44c55491a10693535a79627c478 The Allwinner SoCs have a handful of SRAM that can be either mapped to be accessible by devices or the CPU. That mapping is controlled by an SRAM controller, and that mapping might not be set by the bootloader, for example if the device wasn't used at all, or if we're using solutions like the U-Boot's Falcon Boot. We could also imagine changing this at runtime for example to change the mapping of these SRAMs to use them for suspend/resume or runtime memory rate change, if that ever happens. These use cases require some API in the kernel to control that mapping, exported through a drivers/soc driver. This driver also implement a debugfs file that shows the SRAM found in the system, the current mapping and the SRAM that have been claimed by some drivers in the kernel. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Hans de Goede <hdegoede@redhat.com> Tested-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> 
The Allwinner SoCs have a handful of SRAM that can be either mapped to be
accessible by devices or the CPU.

That mapping is controlled by an SRAM controller, and that mapping might
not be set by the bootloader, for example if the device wasn't used at all,
or if we're using solutions like the U-Boot's Falcon Boot.

We could also imagine changing this at runtime for example to change the
mapping of these SRAMs to use them for suspend/resume or runtime memory
rate change, if that ever happens.

These use cases require some API in the kernel to control that mapping,
exported through a drivers/soc driver.

This driver also implement a debugfs file that shows the SRAM found in the
system, the current mapping and the SRAM that have been claimed by some
drivers in the kernel.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Tested-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc 2015-04-22T16:18:17+00:00 Linus Torvalds torvalds@linux-foundation.org 2015-04-22T16:18:17+00:00 7d2b6ef19cf0f98cef17aa5185de3631a618710a Pull ARM SoC driver updates from Olof Johansson: "Driver updates for v4.1. Some of these are for drivers/soc, where we find more and more SoC-specific drivers these days. Some are for other driver subsystems where we have received acks from the appropriate maintainers. The larger parts of this branch are: - MediaTek support for their PMIC wrapper interface, a high-level interface for talking to the system PMIC over a dedicated I2C interface. - Qualcomm SCM driver has been moved to drivers/firmware. It's used for CPU up/down and needs to be in a shared location for arm/arm64 common code. - cleanup of ARM-CCI PMU code. - another set of cleanusp to the OMAP GPMC code" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (43 commits) soc/mediatek: Remove unused variables clocksource: atmel-st: select MFD_SYSCON soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs arm-cci: Fix CCI PMU event validation arm-cci: Split the code for PMU vs driver support arm-cci: Get rid of secure transactions for PMU driver arm-cci: Abstract the CCI400 PMU specific definitions arm-cci: Rearrange code for splitting PMU vs driver code drivers: cci: reject groups spanning multiple HW PMUs ARM: at91: remove useless include clocksource: atmel-st: remove mach/hardware dependency clocksource: atmel-st: use syscon/regmap ARM: at91: time: move the system timer driver to drivers/clocksource ARM: at91: properly initialize timer ARM: at91: at91rm9200: remove deprecated arm_pm_restart watchdog: at91rm9200: implement restart handler watchdog: at91rm9200: use the system timer syscon mfd: syscon: Add atmel system timer registers definition ARM: at91/dt: declare atmel,at91rm9200-st as a syscon soc: qcom: gsbi: Add support for ADM CRCI muxing ... 
Pull ARM SoC driver updates from Olof Johansson:
 "Driver updates for v4.1.  Some of these are for drivers/soc, where we
  find more and more SoC-specific drivers these days.  Some are for
  other driver subsystems where we have received acks from the
  appropriate maintainers.

  The larger parts of this branch are:

   - MediaTek support for their PMIC wrapper interface, a high-level
     interface for talking to the system PMIC over a dedicated I2C
     interface.

   - Qualcomm SCM driver has been moved to drivers/firmware.  It's used
     for CPU up/down and needs to be in a shared location for arm/arm64
     common code.

   - cleanup of ARM-CCI PMU code.

   - another set of cleanusp to the OMAP GPMC code"

* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (43 commits)
  soc/mediatek: Remove unused variables
  clocksource: atmel-st: select MFD_SYSCON
  soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs
  arm-cci: Fix CCI PMU event validation
  arm-cci: Split the code for PMU vs driver support
  arm-cci: Get rid of secure transactions for PMU driver
  arm-cci: Abstract the CCI400 PMU specific definitions
  arm-cci: Rearrange code for splitting PMU vs driver code
  drivers: cci: reject groups spanning multiple HW PMUs
  ARM: at91: remove useless include
  clocksource: atmel-st: remove mach/hardware dependency
  clocksource: atmel-st: use syscon/regmap
  ARM: at91: time: move the system timer driver to drivers/clocksource
  ARM: at91: properly initialize timer
  ARM: at91: at91rm9200: remove deprecated arm_pm_restart
  watchdog: at91rm9200: implement restart handler
  watchdog: at91rm9200: use the system timer syscon
  mfd: syscon: Add atmel system timer registers definition
  ARM: at91/dt: declare atmel,at91rm9200-st as a syscon
  soc: qcom: gsbi: Add support for ADM CRCI muxing
  ...
dt-bindings: ARM: Mediatek: document binding for the PMIC wrapper 2015-03-30T10:26:35+00:00 Sascha Hauer s.hauer@pengutronix.de 2015-03-17T10:14:33+00:00 979275897e5c52945ae10adba98453cf9e2715d2 This adds documentation for the PMIC wrapper unit found on Mediatek SoCs. Currently support are the MT8135 and MT8173 SoCs, but the PMIC wrapper can also be found on MT6xxx and possibly other SoCs. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com> 
This adds documentation for the PMIC wrapper unit found on Mediatek
SoCs. Currently support are the MT8135 and MT8173 SoCs, but the PMIC
wrapper can also be found on MT6xxx and possibly other SoCs.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
soc: qcom: gsbi: Add support for ADM CRCI muxing 2015-03-11T20:18:39+00:00 Andy Gross agross@codeaurora.org 2015-02-09T22:01:06+00:00 e5fdad68d47ed344832b7ca4e18b2e9708d8141e This patch adds automatic configuration for the ADM CRCI muxing required to support DMA operations for GSBI clients. The GSBI mode and instance determine the correct TCSR ADM CRCI MUX value that must be programmed so that the DMA works properly. Signed-off-by: Andy Gross <agross@codeaurora.org> Signed-off-by: Kumar Gala <galak@codeaurora.org> 
This patch adds automatic configuration for the ADM CRCI muxing required to
support DMA operations for GSBI clients.  The GSBI mode and instance determine
the correct TCSR ADM CRCI MUX value that must be programmed so that the DMA
works properly.

Signed-off-by: Andy Gross <agross@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
dt/bindings: b/qman: Add phandle to the portals 2015-01-30T04:57:44+00:00 Emil Medve Emilian.Medve@freescale.com 2014-12-08T10:29:17+00:00 7af98c7c4dffaf5b0a082fa9c42785d7807e6235 This supports SoC(s) with multiple B/QMan instances Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com> 
This supports SoC(s) with multiple B/QMan instances

Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
dt/bindings: b/qman: Fix the alloc-ranges in the example(s) 2015-01-30T04:57:44+00:00 Emil Medve Emilian.Medve@freescale.com 2014-12-08T10:29:16+00:00 1ee9df499b270f259adc8df9cca396d5ef6e9e46 'ranges' are specified as <base size> not as <start end> Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com> 
'ranges' are specified as <base size> not as <start end>

Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
dt/bindings: Introduce the FSL QorIQ DPAA QMan portal(s) 2014-11-13T05:53:47+00:00 Emil Medve Emilian.Medve@freescale.com 2014-11-05T15:18:54+00:00 f3f6743d1b719ba53aa69493bf76b76a8871bbfa Portals are memory mapped interfaces to QMan that allow low-latency, lock-less interaction by software running on processor cores, accelerators and network interfaces with the QMan Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Change-Id: I29764fa8093b5ce65460abc879446795c50d7185 Signed-off-by: Scott Wood <scottwood@freescale.com> 
Portals are memory mapped interfaces to QMan that allow low-latency,
lock-less interaction by software running on processor cores,
accelerators and network interfaces with the QMan

Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
Change-Id: I29764fa8093b5ce65460abc879446795c50d7185
Signed-off-by: Scott Wood <scottwood@freescale.com>
dt/bindings: Introduce the FSL QorIQ DPAA QMan 2014-11-13T05:53:44+00:00 Emil Medve Emilian.Medve@freescale.com 2014-11-05T15:18:53+00:00 76a4f03f3ec7221112c20d053a1233540a601473 The Queue Manager is part of the Data-Path Acceleration Architecture (DPAA). QMan supports queuing and QoS scheduling of frames to CPUs, network interfaces and DPAA logic modules, maintains packet ordering within flows. Besides providing flow-level queuing, is also responsible for congestion management functions such as RED/WRED, congestion notifications and tail discards. This binding covers the CCSR space programming model Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Change-Id: I3acb223893e42003d6c9dc061db568ec0b10d29b Signed-off-by: Scott Wood <scottwood@freescale.com> 
The Queue Manager is part of the Data-Path Acceleration Architecture
(DPAA).  QMan supports queuing and QoS scheduling of frames to CPUs,
network interfaces and DPAA logic modules, maintains packet ordering
within flows.  Besides providing flow-level queuing, is also
responsible for congestion management functions such as RED/WRED,
congestion notifications and tail discards.  This binding covers the
CCSR space programming model

Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
Change-Id: I3acb223893e42003d6c9dc061db568ec0b10d29b
Signed-off-by: Scott Wood <scottwood@freescale.com>