Add the missing unevaluatedProperties to disallow extra properties on
the '^conf' nodes.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

The "groups" property can hold multiple entries (e.g.
toshiba/tmpv7708-rm-mbrc.dts file), so allow that by dropping incorrect
type (pinmux-node.yaml schema already defines that as string-array) and
adding constraints for items.  This fixes dtbs_check warnings like:

  toshiba/tmpv7708-rm-mbrc.dtb: pinctrl@24190000 (toshiba,tmpv7708-pinctrl):
    pwm-pins:groups: ['pwm0_gpio16_grp', 'pwm1_gpio17_grp', 'pwm2_gpio18_grp', 'pwm3_gpio19_grp'] is too long

Fixes: 1825c1fe0057 ("pinctrl: Add DT bindings for Toshiba Visconti TMPV7700 SoC")
Cc: stable@vger.kernel.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

Pull SoC driver updates from Arnd Bergmann:
 "Lots of platform specific updates for Qualcomm SoCs, including a new
  TEE subsystem driver for the Qualcomm QTEE firmware interface.

  Added support for the Apple A11 SoC in drivers that are shared with
  the M1/M2 series, among more updates for those.

  Smaller platform specific driver updates for Renesas, ASpeed,
  Broadcom, Nvidia, Mediatek, Amlogic, TI, Allwinner, and Freescale
  SoCs.

  Driver updates in the cache controller, memory controller and reset
  controller subsystems.

  SCMI firmware updates to add more features and improve robustness.
  This includes support for having multiple SCMI providers in a single
  system.

  TEE subsystem support for protected DMA-bufs, allowing hardware to
  access memory areas that managed by the kernel but remain inaccessible
  from the CPU in EL1/EL0"

* tag 'soc-drivers-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (139 commits)
  soc/fsl/qbman: Use for_each_online_cpu() instead of for_each_cpu()
  soc: fsl: qe: Drop legacy-of-mm-gpiochip.h header from GPIO driver
  soc: fsl: qe: Change GPIO driver to a proper platform driver
  tee: fix register_shm_helper()
  pmdomain: apple: Add "apple,t8103-pmgr-pwrstate"
  dt-bindings: spmi: Add Apple A11 and T2 compatible
  serial: qcom-geni: Load UART qup Firmware from linux side
  spi: geni-qcom: Load spi qup Firmware from linux side
  i2c: qcom-geni: Load i2c qup Firmware from linux side
  soc: qcom: geni-se: Add support to load QUP SE Firmware via Linux subsystem
  soc: qcom: geni-se: Cleanup register defines and update copyright
  dt-bindings: qcom: se-common: Add QUP Peripheral-specific properties for I2C, SPI, and SERIAL bus
  Documentation: tee: Add Qualcomm TEE driver
  tee: qcom: enable TEE_IOC_SHM_ALLOC ioctl
  tee: qcom: add primordial object
  tee: add Qualcomm TEE driver
  tee: increase TEE_MAX_ARG_SIZE to 4096
  tee: add TEE_IOCTL_PARAM_ATTR_TYPE_OBJREF
  tee: add TEE_IOCTL_PARAM_ATTR_TYPE_UBUF
  tee: add close_context to TEE driver operation
  ...

Pull devicetree updates from Rob Herring:
 "DT core:

   - Update dtc to upstream version v1.7.2-35-g52f07dcca47c

   - Add stub for of_get_next_child_with_prefix()

   - Convert of_msi_map_id() callers to of_msi_xlate()

 DT bindings:

   - Convert multiple text board bindings to DT schema format

   - Add bindings for synaptics,synaptics_i2c touchscreen controller,
     innolux,n133hse-ea1 and nlt,nl12880bc20-spwg-24 displays, and NXP
     vf610 reboot controller

   - Add new Arm Cortex-A320/A520AE/A720AE and C1-Nano/Pro/Premium/Ultra
     CPUs. Add missing Applied Micro CPU compatibles. Add pu-supply and
     fsl,soc-operating-points properties for CPU nodes.

   - Add QCom Glymur PDC and tegra264-agic interrupt controllers

   - Add samsung,exynos8890-mali GPU to Arm Mali Midgard

   - Drop Samsung S3C2410 display related bindings

   - Allow separate DP lane and AUX connections in dp-connector

   - Add some missing, undocumented vendor prefixes

   - Add missing '#address-cells' properties in interrupt controller
     bindings which dtc now warns about

   - Drop duplicate socfpga-sdram-edac.txt, moxa,moxart-watchdog.txt,
     fsl/mpic.txt, ti,opa362.txt, and cavium-thunder2.txt legacy text
     bindings which are already covered by existing schemas.

   - Various binding fixes for Mediatek platforms in mailbox, regulator,
     pinctrl, timer, and display

   - Drop work-around for yamllint quoting of values containing ','

   - Various spelling, typo, grammar, and duplicated words fixes in DT
     bindings and docs

   - Add binding guidelines for defining properties at top level of
     schemas, lack of node name ABI, and usage of simple-mfd"

* tag 'devicetree-for-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (81 commits)
  dt-bindings: arm: altera: Drop socfpga-sdram-edac.txt
  dt-bindings: gpu: Convert nvidia,gk20a to DT schema
  dt-bindings: rng: sparc_sun_oracle_rng: convert to DT schema
  dt-bindings: vendor-prefixes: update regex for properties without a prefix
  dt-bindings: display: bridge: convert megachips-stdpxxxx-ge-b850v3-fw.txt to yaml
  scripts: dt_to_config: fix grammar and a typo in --help text
  dt-bindings: fix spelling, typos, grammar, duplicated words
  docs: dt: fix grammar and spelling
  of: base: Add of_get_next_child_with_prefix() stub
  dt-bindings: trivial-devices: Add compatible string synaptics,synaptics_i2c
  dt-bindings: soc: mediatek: pwrap: Add power-domains property
  dt-bindings: pinctrl: mt65xx: Allow gpio-line-names
  dt-bindings: media: Convert MediaTek mt8173-vpu bindings to DT schema
  dt-bindings: arm: mediatek: Support mt8183-audiosys variant
  dt-bindings: mailbox: mediatek,gce-mailbox: Make clock-names optional
  dt-bindings: regulator: mediatek,mt6331: Add missing compatible
  dt-bindings: regulator: mediatek,mt6331: Fix various regulator names
  dt-bindings: regulator: mediatek,mt6332-regulator: Add missing compatible
  dt-bindings: pinctrl: mediatek,mt7622-pinctrl: Add missing base reg
  dt-bindings: pinctrl: mediatek,mt7622-pinctrl: Add missing pwm_ch7_2
  ...

Pull pin control updates from Linus Walleij:
 "We have GPIO awareness in the pin control core and an interesting
  AAEON driver.

  Core changes:

   - Allow pins to be identified/marked as GPIO mode with a special
     callback.

     The pin controller core is now "aware" if a pin is in GPIO mode if
     the callback is implemented in the driver, and can thus be marked
     as "strict", i.e. disallowing simultaneous use of a line as GPIO
     and another function such as I2C.

     This is enabled in the Qualcomm TLMM driver and also implemeted
     from day 1 in the new Broadcom STB driver

   - Rename the pin config option PIN_CONFIG_OUTPUT to PIN_CONFIG_LEVEL
     to better describe what the config is doing, as well as making it
     more intuitive what shall be returned when reading this property

  New drivers:

   - Qualcomm SDM660 LPASS LPI TLMM pin controller subdriver

   - Qualcomm Glymur family pin controller driver

   - Broadcom STB family pin controller driver

   - Tegra186 pin controller driver

   - AAEON UP pin controller support.

     This is some special pin controller that works as an external
     advanced line MUX and amplifier for signals from an Intel SoC. A
     cooperative effort with the GPIO maintainer was needed to reach a
     solution where we reuse code from the GPIO aggregator/forwarder
     driver

   - Renesas RZ/T2H and RZ/N2H pin controller support

   - Axis ARTPEC-8 subdriver for the Samsung pin controller driver

  Improvements:

   - Output enable (OEN) support in the Renesas RZG2L driver

   - Properly support bias pull up/down in the pinctrl-single driver

   - Move over all GPIO portions using generic MMIO GPIO to the new
     generic GPIO chip management which has a nice and separate API

   - Proper DT bindings for some older Broadcom SoCs

   - External GPIO (EGPIO) support in the Qualcomm SM8250

  Deleted code:

   - Dropped the now unused Samsung S3C24xx drivers"

* tag 'pinctrl-v6.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (75 commits)
  pinctrl: use more common syntax for compound literals
  pinctrl: Simplify printks with pOF format
  pinctrl: qcom: Add SDM660 LPASS LPI TLMM
  dt-bindings: pinctrl: qcom: Add SDM660 LPI pinctrl
  pinctrl: qcom: lpass-lpi: Add ability to use custom pin offsets
  pinctrl: qcom: Add glymur pinctrl driver
  dt-bindings: pinctrl: qcom: Add Glymur pinctrl
  pinctrl: qcom: sm8250: Add egpio support
  pinctrl: generic: rename PIN_CONFIG_OUTPUT to LEVEL
  pinctrl: keembay: fix double free in keembay_build_functions()
  pinctrl: spacemit: fix typo in PRI_TDI pin name
  pinctrl: eswin: Fix regulator error check and Kconfig dependency
  pinctrl: bcm: Add STB family pin controller driver
  dt-bindings: pinctrl: Add support for Broadcom STB pin controller
  pinctrl: qcom: make the pinmuxing strict
  pinctrl: qcom: mark the `gpio` and `egpio` pins function as non-strict functions
  pinctrl: qcom: add infrastructure for marking pin functions as GPIOs
  pinctrl: allow to mark pin functions as requestable GPIOs
  pinctrl: qcom: use generic pin function helpers
  pinctrl: make struct pinfunction a pointer in struct function_desc
  ...

Current, the DT bindings for MediaTek's MT65xx Pin controller is missing
the gpio-line-names property, add it to the associated schema.

Signed-off-by: Ariel D'Alessandro <ariel.dalessandro@collabora.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>

The pin controller for both MT7622 and MT7629 need both a "base"
and an "eint" MMIO like the ones found on other MediaTek SoCs:
while devicetrees have always been correct, the binding is not,
as it only allows an "eint" reg.

Add "base" to reg-names and increment maxItems for reg to two.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>

The MT7622 SoC has a PWM channel 7-2 group for the pwm7 IP: add
the missing pwm_ch7_2 group.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>

After discussion with the devicetree maintainers we agreed to not extend
lists with the generic compatible "apple,pinctrl" anymore [1]. Use
"apple,t8103-pinctrl" as fallback compatible as it is the SoC the driver
and bindings were written for.

The M2 Pro/Max/Ultra SoCs use the same pinctrl hardware, so just add its
per-SoC compatible using the new base as fallback.

[1]: https://lore.kernel.org/asahi/12ab93b7-1fc2-4ce0-926e-c8141cfe81bf@kernel.org/

Acked-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Neal Gompa <neal@gompa.dev>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Janne Grunau <j@jannau.net>

Samsung pinctrl drivers changes for v6.18

1. Add pin controller drivers for new Axis ARTPEC-8 SoC.  The SoC shares
   all main blocks, including the pin controller, with Samsung SoC, so
   same drivers and bindings are used.

2. Drop remaining support for Samsung S3C2410 SoC pin controllers.  The
   actual SoC support was removed in January 2023, so this is just
   remaining cleanup.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>