linux-stable.git/Documentation/devicetree/bindings/phy, branch v5.2

dt-bindings: phy-qcom-qmp: Tweak qcom,msm8998-qmp-ufs-phy

2019-04-22T11:44:39+00:00

Fixup MSM8998 UFS binding now that Evan's reset series has landed.
https://lore.kernel.org/lkml/20190321171800.104681-1-evgreen@chromium.org/

Signed-off-by: Marc Gonzalez 
Signed-off-by: Kishon Vijay Abraham I

dt-bindings: phy-qcom-qmp: Add qcom,msm8998-qmp-pcie-phy

2019-04-18T16:40:52+00:00

Add compatible string for QMP PCIe phy on msm8998.

Signed-off-by: Marc Gonzalez 
Signed-off-by: Kishon Vijay Abraham I

dt-bindings: phy: Add support for HiSilicon's hi3660 USB PHY

2019-04-18T16:38:25+00:00

This patch adds binding documentation for supporting the hi3660 usb
phy on boards like the HiKey960.

Cc: Rob Herring 
Cc: Mark Rutland 
Cc: John Stultz 
Cc: Binghui Wang 
Reviewed-by: Rob Herring 
Signed-off-by: Yu Chen 
Signed-off-by: Kishon Vijay Abraham I

dt-bindings: phy-imx8mq-usb: add optional vbus supply regulator

2019-04-18T16:38:25+00:00

Add a vbus supply regulator phandle, so the PHY can enable the VBUS
voltage rail when powering up.

Signed-off-by: Lucas Stach 
Signed-off-by: Kishon Vijay Abraham I

dt-bindings: phy: ti: Add dt binding documentation for SERDES in AM654x SoC

2019-04-17T08:43:18+00:00

AM654x has two SERDES instances. Each instance has three input clocks
(left input, externel reference clock and right input) and two output
clocks (left output and right output) in addition to a PLL mux clock
which the SERDES uses for Clock Multiplier Unit (CMU refclock).
The PLL mux clock can select from one of the three input clocks.
The right output can select between left input and external reference
clock while the left output can select between the right input and
external reference clock.

The left and right input reference clock of SERDES0 and SERDES1
respectively are connected to the SoC clock. In the case of two lane
SERDES personality card, the left input of SERDES1 is connected to
the right output of SERDES0 in a chained fashion.

See section "Reference Clock Distribution" of AM65x Sitara Processors
TRM (SPRUID7 – April 2018) for more details.

Add dt-binding documentation in order to represent all these different
configurations in device tree.

Signed-off-by: Kishon Vijay Abraham I

dt-bindings: phy: rcar-gen3-phy-usb2: Revise #phy-cells property

2019-04-17T08:43:12+00:00

To have the detailed property on each PHY specifier, this patch revises
the #phy-cells property.

Signed-off-by: Yoshihiro Shimoda 
Signed-off-by: Kishon Vijay Abraham I

dt-bindings: rcar-gen3-phy-usb2: Add r8a77470 support

2019-04-17T08:43:10+00:00

Document RZ/G1C (R8A77470) SoC bindings.

For RZ/G1C, this driver is used to enable interrupt generation and
initializing timing registers which is part of phy_init code.

Signed-off-by: Biju Das 
Reviewed-by: Rob Herring 
Reviewed-by: Yoshihiro Shimoda 
Signed-off-by: Kishon Vijay Abraham I

dt-bindings: phy: rcar-gen2: Add r8a77470 support

2019-04-17T08:43:08+00:00

Add USB PHY support for r8a77470 SoC. Renesas RZ/G1C (R8A77470)
USB PHY is similar to the R-Car Gen2 family, but has the below
feature compared to other RZ/G1 and R-Car Gen2/3 SoCs

It has a shared pll reset for usbphy0/usbphy1 and this register
reside in usbphy0 block.

Signed-off-by: Biju Das 
Reviewed-by: Rob Herring 
Reviewed-by: Yoshihiro Shimoda 
Signed-off-by: Kishon Vijay Abraham I

dt-bindings: phy: Add document for phy-mtk-ufs

2019-04-17T08:43:00+00:00

Add UFS M-PHY node document for MediaTek SoC chips.

Signed-off-by: Stanley Chu 
Reviewed-by: Rob Herring 
Signed-off-by: Kishon Vijay Abraham I

dt-bindings: phy: Add a new property drive-impedance-ohm for RK's emmc PHY

2019-04-17T08:42:59+00:00

This patch documents the new proprty drive-impedance-ohm for
Rockchip's eMMC PHY node.

Signed-off-by: Christoph Muellner 
Signed-off-by: Philipp Tomsich 
Signed-off-by: Kishon Vijay Abraham I