linux-stable.git/Documentation/devicetree/bindings/phy, branch v4.0

phy: miphy365x: Pass sysconfig register offsets via syscfg dt property.

2015-01-30T12:42:05+00:00

Based on Arnds review comments here https://lkml.org/lkml/2014/11/13/161,
update the miphy365 phy driver to access sysconfig register offsets via
syscfg dt property.

This is because the reg property should not be mixing address spaces
like it does currently for miphy365. This change then also aligns us
to how other platforms such as keystone and bcm7445 pass there syscon
offsets via DT.

This patch breaks DT compatibility, but this platform is considered WIP,
and is only used by a few developers who are upstreaming support for it.
This change has been done as a single atomic commit to ensure it is
bisectable.

Signed-off-by: Peter Griffin 
Reviewed-by: Arnd Bergmann 
Acked-by: Maxime Coquelin 
Tested-by: Maxime Coquelin

phy: exynos-video-mipi: Fix regression by adding support for PMU regmap

2015-01-30T10:36:48+00:00

After the Exynos Power Management Unit (PMU) driver was converted
to the platform device driver in commit 14fc8b93d47323561edf5d482
("ARM: EXYNOS: Add platform driver support for Exynos PMU") and
then PMU device nodes added to Exynos4 DTs in commit
7b9613aca42a5522d269 ("ARM: dts: add PMU syscon node for exynos4")
the mipi video phy driver started failing probing, due to overlapping
memory mapped register region resources.

Now all the Exynos peripheral devices which have registers in the PMU
region are supposed to use the regmap provided by the syscon driver.
So support for regmap is added in this patch, this unfortunately
creates yet another indirection into that supposedly trivial driver.

The additional mutex is required because single register is used by
PHY pairs (they share bit in a register). An improvement here could
be to allow a PHY instance be created with a driver custom mutex,
which would then be common for each PHY pair. This would eliminate
one of 3 mutexes which need to be taken in the phy_power_on/
phy_power_off code path. However, I tried to keep this bug fix patch
possibly simple.

This change is needed to make MIPI DSI displays and MIPI CSI-2
camera sensors working again on Exynos4 boards.

Cc: Pankaj Dubey 
Cc: Kukjin Kim 
Signed-off-by: Sylwester Nawrocki 
Signed-off-by: Kishon Vijay Abraham I

Documentation: bindings: add dt documentation for Rockchip usb PHY

2015-01-30T10:36:47+00:00

This patch adds a binding that describes the Rockchip usb PHYs
found on Rockchip SoCs usb interface.

Signed-off-by: Yunzhi Li 
Signed-off-by: Kishon Vijay Abraham I

phy: phy-stih407-usb: Pass sysconfig register offsets via syscfg property.

2015-01-21T09:53:06+00:00

Based on Arnds review comments here https://lkml.org/lkml/2014/11/13/161,
update the phy driver to not use the reg property to access the sysconfig
register offsets.

This is because other phy's (miphy28, miphy365) have a combination of
memory mapped registers and sysconfig control regs, and we shouldn't
be mixing address spaces in the reg property. In addition we would
ideally like the sysconfig offsets to be passed via DT in a uniform way.

This new method will also allow us to support devices which have sysconfig
registers in different banks more easily and it is also analagous to how
keystone and bcm7745 platforms pass there syscon offsets in DT.

This breaks DT compatibility, but this platform is considered WIP, and
is only used by a few developers who are upstreaming support for it.

Signed-off-by: Peter Griffin 
Reviewed-by: Arnd Bergmann 
Signed-off-by: Maxime Coquelin 
Signed-off-by: Kishon Vijay Abraham I

phy: miphy28lp: Pass sysconfig register offsets via syscfg dt property.

2015-01-21T09:53:06+00:00

Based on Arnds review comments here https://lkml.org/lkml/2014/11/13/161,
update the miphy28lp phy driver to access sysconfig register offsets via
syscfg dt property.

This is because the reg property should not be mixing address spaces like
it does currently for miphy28lp. This change then also aligns us to how other
platforms such as keystone and bcm7445 pass there syscon offsets via DT.

I have updated the miphy28lp phy driver same way as Peter's implementation.

Signed-off-by: Gabriel Fernandez 
Signed-off-by: Kishon Vijay Abraham I

Phy: DT binding documentation for the Armada 375 USB cluster binding

2014-11-26T05:37:13+00:00

Armada 375 comes with an USB2 host and device controller and an USB3
controller. The USB cluster control register allows to manage common
features of both USB controllers. This commit adds the Device Tree
binding documentation for this piece of hardware.

Signed-off-by: Gregory CLEMENT 
Acked-by: Jason Cooper 
Signed-off-by: Kishon Vijay Abraham I

Phy: DT binding documentation for Marvell MVEBU SATA phy.

2014-11-26T05:37:13+00:00

Describe the binding for the Marvell MVEBU SATA phy. This driver
can be used at least with Kirkwood, Dove and maybe others.
Additionally, update the SATA binding with the properties to link
to the phy nodes.

Signed-off-by: Andrew Lunn 
Acked-by: Jason Cooper 
Signed-off-by: Kishon Vijay Abraham I

phy: exynos5-usbdrd: Add pipe-clk, utmi-clk and itp-clk support

2014-11-22T08:38:09+00:00

Exynos7 SoC has now separate gate control for 125MHz pipe3 phy
clock, as well as 60MHz utmi phy clock.
Additionally, separate gate control is available for the clock
used for ITP (Isochronous Transfer Packet) generation.

So get the same and control in the phy-exynos5-usbdrd driver.

Suggested-by: Anton Tikhomirov 
Signed-off-by: Vivek Gautam 
Signed-off-by: Kishon Vijay Abraham I

Documentation: bindings: add doc for the Berlin USB PHY

2014-11-21T14:18:50+00:00

Document the bindings of the Marvell Berlin USB PHY driver.

Signed-off-by: Antoine Tenart 
Signed-off-by: Kishon Vijay Abraham I

phy: berlin-sata: Document BG2 compatible

2014-11-13T06:19:44+00:00

Berlin BG2 SATA PHY is slightly different from currently supported
BG2Q SATA PHY. Document the new compatible for BG2's PHY.

Acked-by: Antoine Ténart 
Signed-off-by: Sebastian Hesselbarth 
Signed-off-by: Kishon Vijay Abraham I