linux-stable.git/Documentation/devicetree/bindings/phy, branch linux-6.9.y Linux kernel stable tree dt-bindings: phy: qcom,usb-snps-femto-v2: use correct fallback for sc8180x 2024-06-12T09:39:17+00:00 Dmitry Baryshkov dmitry.baryshkov@linaro.org 2024-05-01T16:19:29+00:00 ad852483eb3905b5ddc55bc72ddcb26de9da929b [ Upstream commit 960b3f023d3bda0efd6e573a0647227d1115d266 ] The qcom,sc8180x-usb-hs-phy device uses qcom,usb-snps-hs-7nm-phy fallback. Correct the schema for this platform. Fixes: 9160fb7c39a1 ("dt-bindings: phy: qcom,usb-snps-femto-v2: use fallback compatibles") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240501-qcom-phy-fixes-v1-3-f1fd15c33fb3@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org> 
[ Upstream commit 960b3f023d3bda0efd6e573a0647227d1115d266 ]

The qcom,sc8180x-usb-hs-phy device uses qcom,usb-snps-hs-7nm-phy
fallback. Correct the schema for this platform.

Fixes: 9160fb7c39a1 ("dt-bindings: phy: qcom,usb-snps-femto-v2: use fallback compatibles")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240501-qcom-phy-fixes-v1-3-f1fd15c33fb3@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: fix msm899[68] power-domains 2024-06-12T09:39:16+00:00 Dmitry Baryshkov dmitry.baryshkov@linaro.org 2024-05-01T16:19:28+00:00 f19c2b0e9fdc758f9504ff6593ff5ac7fed1512b [ Upstream commit 59e377a124dc9039d9554d823b1cb4942bcee9a0 ] The Qualcomm MSM8996 and MSM8998 platforms don't have separate power domain for the UFS PHY. Replace required:power-domains with the conditional schema. Fixes: dc5cb63592bd ("dt-bindings: phy: migrate QMP UFS PHY bindings to qcom,sc8280xp-qmp-ufs-phy.yaml") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240501-qcom-phy-fixes-v1-2-f1fd15c33fb3@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org> 
[ Upstream commit 59e377a124dc9039d9554d823b1cb4942bcee9a0 ]

The Qualcomm MSM8996 and MSM8998 platforms don't have separate power
domain for the UFS PHY. Replace required:power-domains with the
conditional schema.

Fixes: dc5cb63592bd ("dt-bindings: phy: migrate QMP UFS PHY bindings to qcom,sc8280xp-qmp-ufs-phy.yaml")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240501-qcom-phy-fixes-v1-2-f1fd15c33fb3@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: fix x1e80100-gen3x2 schema 2024-06-12T09:39:16+00:00 Dmitry Baryshkov dmitry.baryshkov@linaro.org 2024-05-01T16:19:27+00:00 ad855902d2d4f278ce992d646fd87f4a3b4474b6 [ Upstream commit 484b139a4cd7e629f8fcb43d71997f400c5b8537 ] The qcom,x1e80100-qmp-gen3x2-pcie-phy device doesn't have second reset, drop it from the clause enforcing second reset to be used. Fixes: e94b29f2bd73 ("dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the X1E80100 QMP PCIe PHYs") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240501-qcom-phy-fixes-v1-1-f1fd15c33fb3@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org> 
[ Upstream commit 484b139a4cd7e629f8fcb43d71997f400c5b8537 ]

The qcom,x1e80100-qmp-gen3x2-pcie-phy device doesn't have second reset,
drop it from the clause enforcing second reset to be used.

Fixes: e94b29f2bd73 ("dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the X1E80100 QMP PCIe PHYs")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240501-qcom-phy-fixes-v1-1-f1fd15c33fb3@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
dt-bindings: phy: Add Rockchip HDMI/eDP Combo PHY schema 2024-02-16T06:56:56+00:00 Cristian Ciocaltea cristian.ciocaltea@collabora.com 2024-02-14T11:45:36+00:00 3312a0e8f64ec68db695224fcc7457e7292426eb Add dt-binding schema for the HDMI/eDP Transmitter Combo PHY found on Rockchip RK3588 SoC. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://lore.kernel.org/r/20240214-phy-hdptx-v4-1-e7974f46c1a7@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org> 
Add dt-binding schema for the HDMI/eDP Transmitter Combo PHY found on
Rockchip RK3588 SoC.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Link: https://lore.kernel.org/r/20240214-phy-hdptx-v4-1-e7974f46c1a7@collabora.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
dt-bindings: phy: add mediatek MIPI CD-PHY module v0.5 2024-02-07T14:02:13+00:00 Florian Sylvestre fsylvestre@baylibre.com 2024-01-11T10:14:50+00:00 a41baa4f0f7d215f4c95a053f593d9b1378963f7 This adds the bindings, for the MIPI CD-PHY module v0.5 embedded in some Mediatek soc, such as the mt8365 Signed-off-by: Florian Sylvestre <fsylvestre@baylibre.com> Signed-off-by: Julien Stephan <jstephan@baylibre.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20240111101504.468169-2-jstephan@baylibre.com Signed-off-by: Vinod Koul <vkoul@kernel.org> 
This adds the bindings, for the MIPI CD-PHY module v0.5 embedded in
some Mediatek soc, such as the mt8365

Signed-off-by: Florian Sylvestre <fsylvestre@baylibre.com>
Signed-off-by: Julien Stephan <jstephan@baylibre.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20240111101504.468169-2-jstephan@baylibre.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
dt-bindings: phy: cadence-torrent: Add a separate compatible for TI J7200 2024-02-07T14:02:13+00:00 Swapnil Jakhade sjakhade@cadence.com 2024-01-04T13:30:12+00:00 dc44dac3a787d55c26991d56a605c606b8ec3960 TI J7200 uses Torrent SD0805 version which is a special version derived from Torrent SD0801 with some differences in register configurations. Add a separate compatible for TI J7200 platforms. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20240104133013.2911035-5-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org> 
TI J7200 uses Torrent SD0805 version which is a special version derived
from Torrent SD0801 with some differences in register configurations.
Add a separate compatible for TI J7200 platforms.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20240104133013.2911035-5-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
dt-bindings: phy: cadence-torrent: Add optional input reference clock for PLL1 2024-02-07T14:02:13+00:00 Swapnil Jakhade sjakhade@cadence.com 2024-01-04T13:30:09+00:00 088de1293c84d0c08f0f4c30d2dd7cb14888aa6c Add a new optional input reference clock (pll1_refclk) for PLL1. Update bindings to support dual reference clock multilink configurations. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20240104133013.2911035-2-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org> 
Add a new optional input reference clock (pll1_refclk) for PLL1.
Update bindings to support dual reference clock multilink configurations.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20240104133013.2911035-2-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
dt-bindings: phy: qmp-ufs: Fix PHY clocks 2024-02-07T09:01:52+00:00 Manivannan Sadhasivam manivannan.sadhasivam@linaro.org 2024-01-31T07:07:24+00:00 b0bcec86f47b44c98a23c31d54dd3963e27761a2 All QMP UFS PHYs except MSM8996 require 3 clocks: * ref - 19.2MHz reference clock from RPMh * ref_aux - Auxiliary reference clock from GCC * qref - QREF clock from GCC or TCSR (since SM8550) MSM8996 only requires 'ref' and 'qref' clocks. Hence, fix the binding to reflect the actual clock topology. This change obviously breaks the ABI, but it is inevitable since the clock topology needs to be accurately described in the binding. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20240131-ufs-phy-clock-v3-1-58a49d2f4605@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org> 
All QMP UFS PHYs except MSM8996 require 3 clocks:

* ref - 19.2MHz reference clock from RPMh
* ref_aux - Auxiliary reference clock from GCC
* qref - QREF clock from GCC or TCSR (since SM8550)

MSM8996 only requires 'ref' and 'qref' clocks. Hence, fix the binding to
reflect the actual clock topology.

This change obviously breaks the ABI, but it is inevitable since the
clock topology needs to be accurately described in the binding.

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20240131-ufs-phy-clock-v3-1-58a49d2f4605@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the X1E80100 QMP PCIe PHYs 2024-01-24T05:50:14+00:00 Abel Vesa abel.vesa@linaro.org 2023-12-23T11:55:21+00:00 e94b29f2bd73db149ce7fee9a41a7b6ca17f7918 Document the QMP PCIe PHYs on the X1E80100 platform. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20231223-x1e80100-phy-pcie-v2-1-223c0556908a@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org> 
Document the QMP PCIe PHYs on the X1E80100 platform.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20231223-x1e80100-phy-pcie-v2-1-223c0556908a@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
dt-bindings: phy: qcom,msm8998-qmp-usb3-phy: support SDM660 2024-01-23T14:11:34+00:00 Dmitry Baryshkov dmitry.baryshkov@linaro.org 2024-01-16T01:10:55+00:00 0ca5e2bf2f4753a879ed3f4a747ee5c947152838 Declare the USB-C QMP PHY present on the Qualcomm SDM660 / SDM630 platforms. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240116-sdm660-usb3-support-v1-1-2fbd683aea77@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org> 
Declare the USB-C QMP PHY present on the Qualcomm SDM660 / SDM630
platforms.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240116-sdm660-usb3-support-v1-1-2fbd683aea77@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>