linux-stable.git/Documentation/devicetree/bindings/memory-controllers, branch v4.7

Merge tag 'for-linus-20160523' of git://git.infradead.org/linux-mtd

2016-05-24T18:00:20+00:00

Pull MTD updates from Brian Norris:
 "First cycle with Boris as NAND maintainer! Many (most) bullets stolen
  from him.

  Generic:
   - Migrated NAND LED trigger to be a generic MTD trigger

  NAND:
   - Introduction of the "ECC algorithm" concept, to avoid overloading
     the ECC mode field too much more
   - Replaced the nand_ecclayout infrastructure with something a little
     more flexible (finally!) and future proof
   - Rework of the OMAP GPMC and NAND drivers; the TI folks pulled some
     of this into their own tree as well
   - Prepare the sunxi NAND driver to receive DMA support
   - Handle bitflips in erased pages on GPMI revisions that do not
     support this in hardware.

  SPI NOR:
   - Start using the spi_flash_read() API for SPI drivers that support
     it (i.e., SPI drivers with special memory-mapped flash modes)

  And other small scattered improvments"

* tag 'for-linus-20160523' of git://git.infradead.org/linux-mtd: (155 commits)
  mtd: spi-nor: support GigaDevice gd25lq64c
  mtd: nand_bch: fix spelling of "probably"
  mtd: brcmnand: respect ECC algorithm set by NAND subsystem
  gpmi-nand: Handle ECC Errors in erased pages
  Documentation: devicetree: deprecate "soft_bch" nand-ecc-mode value
  mtd: nand: add support for "nand-ecc-algo" DT property
  mtd: mtd: drop NAND_ECC_SOFT_BCH enum value
  mtd: drop support for NAND_ECC_SOFT_BCH as "soft_bch" mapping
  mtd: nand: read ECC algorithm from the new field
  mtd: nand: fsmc: validate ECC setup by checking algorithm directly
  mtd: nand: set ECC algorithm to Hamming on fallback
  staging: mt29f_spinand: set ECC algorithm explicitly
  CRIS v32: nand: set ECC algorithm explicitly
  mtd: nand: atmel: set ECC algorithm explicitly
  mtd: nand: davinci: set ECC algorithm explicitly
  mtd: nand: bf5xx: set ECC algorithm explicitly
  mtd: nand: omap2: Fix high memory dma prefetch transfer
  mtd: nand: omap2: Start dma request before enabling prefetch
  mtd: nandsim: add __init attribute
  mtd: nand: move of_get_nand_xxx() helpers into nand_base.c
  ...

Merge tag 'devicetree-for-4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux

2016-05-20T21:51:34+00:00

Pull devicetree updates from Rob Herring:

- Rewrite of the unflattening code to avoid recursion and lessen the
stack usage.

- Rewrite of the phandle args parsing code to get rid of the fixed args
size. This is needed for IOMMU code.

- Sync to latest dtc which adds more dts style checking. These
warnings are enabled with "W=1" compiles.

- Tegra documentation updates related to the above warnings.

- A bunch of spelling and other doc fixes.

- Various vendor prefix additions.

* tag 'devicetree-for-4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (52 commits)
devicetree: Add Creative Technology vendor id
gpio: dt-bindings: add ibm,ppc4xx-gpio binding
of/unittest: Remove unnecessary module.h header inclusion
drivers/of: Fix build warning in populate_node()
drivers/of: Fix depth when unflattening devicetree
of: dynamic: changeset prop-update revert fix
drivers/of: Export of_detach_node()
drivers/of: Return allocated memory from of_fdt_unflatten_tree()
drivers/of: Specify parent node in of_fdt_unflatten_tree()
drivers/of: Rename unflatten_dt_node()
drivers/of: Avoid recursively calling unflatten_dt_node()
drivers/of: Split unflatten_dt_node()
of: include errno.h in of_graph.h
of: document refcount incrementation of of_get_cpu_node()
Documentation: dt: soc: fix spelling mistakes
Documentation: dt: power: fix spelling mistake
Documentation: dt: pinctrl: fix spelling mistake
Documentation: dt: opp: fix spelling mistake
Documentation: dt: net: fix spelling mistakes
Documentation: dt: mtd: fix spelling mistake
...

dt-bindings: tegra: Rename some bindings for consistency

2016-04-19T22:25:19+00:00

Device tree binding for NVIDIA Tegra have traditionally carried the
"nvidia," vendor prefix in the filename. A couple of odd ones don't, so
fix them up for consistency.

Also rename existing bindings to reflect the first compatible value that
they document. This wasn't done consistently either.

Acked-by: Stephen Warren 
Signed-off-by: Thierry Reding 
Signed-off-by: Rob Herring

dt-bindings: tegra: Remove 0, prefix from unit-addresses

2016-04-19T22:25:18+00:00

When Tegra124 support was first merged the unit-addresses of all devices
were listed with a "0," prefix to encode the reg property's second cell.
It turns out that this notation is not correct, and the "," separator is
only used to separate fields in the unit address (such as the device and
function number in PCI devices), not individual cells for addresses
with more than one cell.

Acked-by: Stephen Warren 
Signed-off-by: Thierry Reding 
Signed-off-by: Rob Herring

dt-bindings: EXYNOS: Add exynos-srom device tree binding

2016-04-18T12:25:22+00:00

This patch adds exynos-srom binding information for SROM Controller
driver on Exynos SoCs. Documentation for new subnode properties,
allowing bank configuration are added based on u-boot implementation,
but heavily reworked.

CC: Rob Herring 
CC: Mark Rutland 
CC: Ian Campbell 
Signed-off-by: Pankaj Dubey 
[p.fedin: Added SROMc configuration description and fixed SROMc mapping]
Signed-off-by: Pavel Fedin 
Reviewed-by: Krzysztof Kozlowski 
Signed-off-by: Kukjin Kim 
Signed-off-by: Krzysztof Kozlowski

memory: omap-gpmc: Support WAIT pin edge interrupts

2016-04-15T08:55:06+00:00

OMAPs can have 2 to 4 WAITPINs that can be used as edge triggered
interrupts if not used for memory wait state insertion.

Support these interrupts via the gpmc IRQ domain.

The gpmc IRQ domain interrupt map is:

0 - NAND_fifoevent
1 - NAND_termcount
2 - GPMC_WAIT0 edge
3 - GPMC_WAIT1 edge, and so on

Signed-off-by: Roger Quadros 
Acked-by: Rob Herring 
Acked-by: Tony Lindgren

memory: omap-gpmc: Support general purpose input for WAITPINs

2016-04-15T08:54:12+00:00

OMAPs can have 2 to 4 WAITPINs that can be used as general purpose
input if not used for memory wait state insertion.

The first user will be the OMAP NAND chip to get the NAND
read/busy status using gpiolib.

Signed-off-by: Roger Quadros 
Acked-by: Rob Herring 
Acked-by: Tony Lindgren

memory: omap-gpmc: Move device tree binding to correct location

2016-04-15T08:54:03+00:00

omap-gpmc.c is a memory controller so move the binding to the
right place.

Signed-off-by: Roger Quadros 
Acked-by: Rob Herring 
Acked-by: Tony Lindgren

dt-bindings: mediatek: Add smi dts binding

2016-02-25T15:49:08+00:00

This patch add smi binding document and smi local arbiter header file.

Signed-off-by: Yong Wu 
Acked-by: Rob Herring 
Signed-off-by: Joerg Roedel

dt-bindings: Misc fix for the ATH79 DDR controllers

2015-12-09T21:30:55+00:00

Fix a few typos and reword the description of the
'#qca,ddr-wb-channel-cells' property.

Signed-off-by: Alban Bedel 
CC: trivial@kernel.org
Signed-off-by: Rob Herring