<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-stable.git/Documentation/devicetree/bindings/interrupt-controller, branch v4.20</title>
<subtitle>Linux kernel stable tree</subtitle>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/'/>
<entry>
<title>Merge tag 'csky-for-linus-4.20' of https://github.com/c-sky/csky-linux</title>
<updated>2018-10-29T15:25:00+00:00</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2018-10-29T15:25:00+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=ac435075892e3e651c667b4a9f2267cf3ef1d5a2'/>
<id>ac435075892e3e651c667b4a9f2267cf3ef1d5a2</id>
<content type='text'>
Pull C-SKY architecture port from Guo Ren:
 "This contains the Linux port for C-SKY(csky) based on linux-4.19
  Release, which has been through 10 rounds of review on mailing list.

  More information:

    http://en.c-sky.com

  The development repo:

    https://github.com/c-sky/csky-linux

  ABI Documentation:

    https://github.com/c-sky/csky-doc

  Here is the pre-built cross compiler for fast test from our CI:

    https://gitlab.com/c-sky/buildroot/-/jobs/101608095/artifacts/file/output/images/csky_toolchain_qemu_csky_ck807f_4.18_glibc_defconfig_482b221e52908be1c9b2ccb444255e1562bb7025.tar.xz

  We use buildroot as our CI-test enviornment. "LTP, Lmbench ..." will
  be tested for every commit. See here for more details:

    https://gitlab.com/c-sky/buildroot/pipelines

  We'll continouslly improve csky subsystem in future"

Arnd acks, and adds the following notes:
 "I did a thorough review of the ABI, which as usual mainly consists of
  spotting any files that don't use the asm-generic ABI itself, and
  having it changed to it matches exactly what we do on other new
  architectures.

  I also looked at every other patch and commented on maybe half of them
  where I saw something that did not quite seem right. Others have
  reviewed specific patches in greater depth. I'm sure that one could
  fine more of the minor details, but as long as they are not ABI
  relevant, they can be fixed later.

  The only patch that is part of the ABI and that nobody reviewed is the
  signal handling. This is one of the areas I never worked on in much
  detail. I did not see anything wrong with it, but I also don't know
  what the problems with the other architectures are here, and we seem
  to be hitting issues occasionally, and we never managed to generalize
  this enough for new architectures to have a trivial implementation.

  I was originally hoping that we could have the 64-bit time_t
  interfaces ready in time to completely drop the 32-bit ones, but that
  did not happen. We might still remove them in the next merge window
  depending on whether the libc upstream people prefer to keep them or
  not.

  One more general comment: I think this may well be the last new CPU
  architecture we ever add to the kernel. Both nds32 and c-sky are made
  by companies that also work on risc-v, and generally speaking risc-v
  seems to be killing off any of the minor licensable instruction set
  projects, just like ARM has mostly killed off the custom
  vendor-specific instruction sets already.

  If we add another architecture in the future, it may instead be
  something like the LLVM bitcode or WebAssembly, who knows?"

To which Geert Uytterhoeven pipes in about another architecture still in
the pipeline: Kalray MPPA.

* tag 'csky-for-linus-4.20' of https://github.com/c-sky/csky-linux: (24 commits)
  dt-bindings: interrupt-controller: C-SKY APB intc
  irqchip: add C-SKY APB bus interrupt controller
  dt-bindings: interrupt-controller: C-SKY SMP intc
  irqchip: add C-SKY SMP interrupt controller
  MAINTAINERS: Add csky
  dt-bindings: Add vendor prefix for csky
  dt-bindings: csky CPU Bindings
  csky: Misc headers
  csky: SMP support
  csky: Debug and Ptrace GDB
  csky: User access
  csky: Library functions
  csky: ELF and module probe
  csky: Atomic operations
  csky: IRQ handling
  csky: VDSO and rt_sigreturn
  csky: Process management and Signal
  csky: MMU and page table management
  csky: Cache and TLB routines
  csky: System Call
  ...
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Pull C-SKY architecture port from Guo Ren:
 "This contains the Linux port for C-SKY(csky) based on linux-4.19
  Release, which has been through 10 rounds of review on mailing list.

  More information:

    http://en.c-sky.com

  The development repo:

    https://github.com/c-sky/csky-linux

  ABI Documentation:

    https://github.com/c-sky/csky-doc

  Here is the pre-built cross compiler for fast test from our CI:

    https://gitlab.com/c-sky/buildroot/-/jobs/101608095/artifacts/file/output/images/csky_toolchain_qemu_csky_ck807f_4.18_glibc_defconfig_482b221e52908be1c9b2ccb444255e1562bb7025.tar.xz

  We use buildroot as our CI-test enviornment. "LTP, Lmbench ..." will
  be tested for every commit. See here for more details:

    https://gitlab.com/c-sky/buildroot/pipelines

  We'll continouslly improve csky subsystem in future"

Arnd acks, and adds the following notes:
 "I did a thorough review of the ABI, which as usual mainly consists of
  spotting any files that don't use the asm-generic ABI itself, and
  having it changed to it matches exactly what we do on other new
  architectures.

  I also looked at every other patch and commented on maybe half of them
  where I saw something that did not quite seem right. Others have
  reviewed specific patches in greater depth. I'm sure that one could
  fine more of the minor details, but as long as they are not ABI
  relevant, they can be fixed later.

  The only patch that is part of the ABI and that nobody reviewed is the
  signal handling. This is one of the areas I never worked on in much
  detail. I did not see anything wrong with it, but I also don't know
  what the problems with the other architectures are here, and we seem
  to be hitting issues occasionally, and we never managed to generalize
  this enough for new architectures to have a trivial implementation.

  I was originally hoping that we could have the 64-bit time_t
  interfaces ready in time to completely drop the 32-bit ones, but that
  did not happen. We might still remove them in the next merge window
  depending on whether the libc upstream people prefer to keep them or
  not.

  One more general comment: I think this may well be the last new CPU
  architecture we ever add to the kernel. Both nds32 and c-sky are made
  by companies that also work on risc-v, and generally speaking risc-v
  seems to be killing off any of the minor licensable instruction set
  projects, just like ARM has mostly killed off the custom
  vendor-specific instruction sets already.

  If we add another architecture in the future, it may instead be
  something like the LLVM bitcode or WebAssembly, who knows?"

To which Geert Uytterhoeven pipes in about another architecture still in
the pipeline: Kalray MPPA.

* tag 'csky-for-linus-4.20' of https://github.com/c-sky/csky-linux: (24 commits)
  dt-bindings: interrupt-controller: C-SKY APB intc
  irqchip: add C-SKY APB bus interrupt controller
  dt-bindings: interrupt-controller: C-SKY SMP intc
  irqchip: add C-SKY SMP interrupt controller
  MAINTAINERS: Add csky
  dt-bindings: Add vendor prefix for csky
  dt-bindings: csky CPU Bindings
  csky: Misc headers
  csky: SMP support
  csky: Debug and Ptrace GDB
  csky: User access
  csky: Library functions
  csky: ELF and module probe
  csky: Atomic operations
  csky: IRQ handling
  csky: VDSO and rt_sigreturn
  csky: Process management and Signal
  csky: MMU and page table management
  csky: Cache and TLB routines
  csky: System Call
  ...
</pre>
</div>
</content>
</entry>
<entry>
<title>dt-bindings: interrupt-controller: C-SKY APB intc</title>
<updated>2018-10-25T16:54:31+00:00</updated>
<author>
<name>Guo Ren</name>
<email>ren_guo@c-sky.com</email>
</author>
<published>2018-09-05T06:25:23+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=2347e7e1aea410865e3c3f92014b07ff7d4c5b02'/>
<id>2347e7e1aea410865e3c3f92014b07ff7d4c5b02</id>
<content type='text'>
 - Dt-bindings doc about C-SKY apb bus interrupt controller.

Signed-off-by: Guo Ren &lt;ren_guo@c-sky.com&gt;
Reviewed-by: Rob Herring &lt;robh@kernel.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
 - Dt-bindings doc about C-SKY apb bus interrupt controller.

Signed-off-by: Guo Ren &lt;ren_guo@c-sky.com&gt;
Reviewed-by: Rob Herring &lt;robh@kernel.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>dt-bindings: interrupt-controller: C-SKY SMP intc</title>
<updated>2018-10-25T16:54:30+00:00</updated>
<author>
<name>Guo Ren</name>
<email>ren_guo@c-sky.com</email>
</author>
<published>2018-09-18T13:07:00+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=3fe5d5bd2dd92124f2a773c19fbc117e023a2ce3'/>
<id>3fe5d5bd2dd92124f2a773c19fbc117e023a2ce3</id>
<content type='text'>
Dt-bindings doc about C-SKY Multi-processors interrupt controller.

Changelog:
 - Should be: '#interrupt-cells' not 'interrupt-cells'

Signed-off-by: Guo Ren &lt;ren_guo@c-sky.com&gt;
Reviewed-by: Rob Herring &lt;robh@kernel.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Dt-bindings doc about C-SKY Multi-processors interrupt controller.

Changelog:
 - Should be: '#interrupt-cells' not 'interrupt-cells'

Signed-off-by: Guo Ren &lt;ren_guo@c-sky.com&gt;
Reviewed-by: Rob Herring &lt;robh@kernel.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>dt-bindings/interrupt-controller: Add documentation for Marvell SEI controller</title>
<updated>2018-10-02T11:02:43+00:00</updated>
<author>
<name>Miquel Raynal</name>
<email>miquel.raynal@bootlin.com</email>
</author>
<published>2018-10-01T14:13:55+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=079f4532008e21d40a2c43eb32df0fdf7d8dbddc'/>
<id>079f4532008e21d40a2c43eb32df0fdf7d8dbddc</id>
<content type='text'>
Describe the System Error Interrupt (SEI) controller. It aggregates two
types of interrupts, wired and MSIs from respectively the AP and the
CPs, into a single SPI interrupt.

Suggested-by: Haim Boot &lt;hayim@marvell.com&gt;
Reviewed-by: Rob Herring &lt;robh@kernel.org&gt;
Signed-off-by: Miquel Raynal &lt;miquel.raynal@bootlin.com&gt;
Signed-off-by: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Describe the System Error Interrupt (SEI) controller. It aggregates two
types of interrupts, wired and MSIs from respectively the AP and the
CPs, into a single SPI interrupt.

Suggested-by: Haim Boot &lt;hayim@marvell.com&gt;
Reviewed-by: Rob Herring &lt;robh@kernel.org&gt;
Signed-off-by: Miquel Raynal &lt;miquel.raynal@bootlin.com&gt;
Signed-off-by: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>dt-bindings/interrupt-controller: Update Marvell ICU bindings</title>
<updated>2018-10-02T11:02:20+00:00</updated>
<author>
<name>Miquel Raynal</name>
<email>miquel.raynal@bootlin.com</email>
</author>
<published>2018-10-01T14:13:54+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=548ce8156f9dc5ca3e09c18f4d5307918a2645b4'/>
<id>548ce8156f9dc5ca3e09c18f4d5307918a2645b4</id>
<content type='text'>
Change the documentation to reflect the new bindings used for Marvell
ICU. This involves describing each interrupt group as a subnode of the
ICU node. Each of them having their own compatible.

The DT binding documentation still documents the legacy binding, where
there was a single node with no subnode.

Reviewed-by: Rob Herring &lt;robh@kernel.org&gt;
Signed-off-by: Miquel Raynal &lt;miquel.raynal@bootlin.com&gt;
Signed-off-by: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Change the documentation to reflect the new bindings used for Marvell
ICU. This involves describing each interrupt group as a subnode of the
ICU node. Each of them having their own compatible.

The DT binding documentation still documents the legacy binding, where
there was a single node with no subnode.

Reviewed-by: Rob Herring &lt;robh@kernel.org&gt;
Signed-off-by: Miquel Raynal &lt;miquel.raynal@bootlin.com&gt;
Signed-off-by: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>dt-bindings/interrupt-controller: Fix Marvell ICU length in the example</title>
<updated>2018-10-02T10:59:14+00:00</updated>
<author>
<name>Miquel Raynal</name>
<email>miquel.raynal@bootlin.com</email>
</author>
<published>2018-10-01T14:13:46+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=018ea8475b601a625ed2bdb8ab62f6b3aafecb9d'/>
<id>018ea8475b601a625ed2bdb8ab62f6b3aafecb9d</id>
<content type='text'>
ICU size in CP110 is not 0x10 but at least 0x440 bytes long (from the
specification).

Reviewed-by: Rob Herring &lt;robh@kernel.org&gt;
Reviewed-by: Thomas Petazzoni &lt;thomas.petazzoni@bootlin.com&gt;
Signed-off-by: Miquel Raynal &lt;miquel.raynal@bootlin.com&gt;
Signed-off-by: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
ICU size in CP110 is not 0x10 but at least 0x440 bytes long (from the
specification).

Reviewed-by: Rob Herring &lt;robh@kernel.org&gt;
Reviewed-by: Thomas Petazzoni &lt;thomas.petazzoni@bootlin.com&gt;
Signed-off-by: Miquel Raynal &lt;miquel.raynal@bootlin.com&gt;
Signed-off-by: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>dt-bindings: irqchip: renesas-irqc: Document r8a7744 support</title>
<updated>2018-10-02T09:37:40+00:00</updated>
<author>
<name>Biju Das</name>
<email>biju.das@bp.renesas.com</email>
</author>
<published>2018-09-25T16:56:34+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=0c4cb97d4ec9d98fc5e30317326f28ed206f3ac6'/>
<id>0c4cb97d4ec9d98fc5e30317326f28ed206f3ac6</id>
<content type='text'>
Document RZ/G1N (R8A7744) SoC bindings.

Reviewed-by: Chris Paterson &lt;Chris.Paterson2@renesas.com&gt;
Reviewed-by: Simon Horman &lt;horms+renesas@verge.net.au&gt;
Reviewed-by: Geert Uytterhoeven &lt;geert+renesas@glider.be&gt;
Signed-off-by: Biju Das &lt;biju.das@bp.renesas.com&gt;
Signed-off-by: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Document RZ/G1N (R8A7744) SoC bindings.

Reviewed-by: Chris Paterson &lt;Chris.Paterson2@renesas.com&gt;
Reviewed-by: Simon Horman &lt;horms+renesas@verge.net.au&gt;
Reviewed-by: Geert Uytterhoeven &lt;geert+renesas@glider.be&gt;
Signed-off-by: Biju Das &lt;biju.das@bp.renesas.com&gt;
Signed-off-by: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>dt-bindings: irqchip: renesas-irqc: Document R-Car E3 support</title>
<updated>2018-10-02T09:37:39+00:00</updated>
<author>
<name>Geert Uytterhoeven</name>
<email>geert+renesas@glider.be</email>
</author>
<published>2018-09-28T11:32:38+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=339794e36d5e3c85f335bfdd3bd26e40c5f5e064'/>
<id>339794e36d5e3c85f335bfdd3bd26e40c5f5e064</id>
<content type='text'>
Document support for the Interrupt Controller for External Devices
(INTC-EX) in the Renesas E3 (r8a77990) SoC.

No driver update is needed.

Signed-off-by: Geert Uytterhoeven &lt;geert+renesas@glider.be&gt;
Signed-off-by: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Document support for the Interrupt Controller for External Devices
(INTC-EX) in the Renesas E3 (r8a77990) SoC.

No driver update is needed.

Signed-off-by: Geert Uytterhoeven &lt;geert+renesas@glider.be&gt;
Signed-off-by: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>dt-bindings: riscv,cpu-intc: Cleanups from a missed review</title>
<updated>2018-08-28T19:58:35+00:00</updated>
<author>
<name>Palmer Dabbelt</name>
<email>palmer@sifive.com</email>
</author>
<published>2018-08-20T22:47:57+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=11f65ad111fa29de2d11929f773bf1e553d5b7c4'/>
<id>11f65ad111fa29de2d11929f773bf1e553d5b7c4</id>
<content type='text'>
I managed to miss one of Rob's code reviews on the mailing list
&lt;http://lists.infradead.org/pipermail/linux-riscv/2018-August/001139.html&gt;.
The patch has already been merged, so I'm submitting a fixup.

Sorry!

Fixes: b67bc7cb4088 ("dt-bindings: interrupt-controller: RISC-V local interrupt controller")
Cc: Rob Herring &lt;robh@kernel.org&gt;
Cc: Christoph Hellwig &lt;hch@infradead.org&gt;
Cc: Karsten Merker &lt;merker@debian.org&gt;
Signed-off-by: Palmer Dabbelt &lt;palmer@sifive.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
I managed to miss one of Rob's code reviews on the mailing list
&lt;http://lists.infradead.org/pipermail/linux-riscv/2018-August/001139.html&gt;.
The patch has already been merged, so I'm submitting a fixup.

Sorry!

Fixes: b67bc7cb4088 ("dt-bindings: interrupt-controller: RISC-V local interrupt controller")
Cc: Rob Herring &lt;robh@kernel.org&gt;
Cc: Christoph Hellwig &lt;hch@infradead.org&gt;
Cc: Karsten Merker &lt;merker@debian.org&gt;
Signed-off-by: Palmer Dabbelt &lt;palmer@sifive.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge branch 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip</title>
<updated>2018-08-26T16:55:28+00:00</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2018-08-26T16:55:28+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=de3750351c0de35472299506ace61a01f2bfc567'/>
<id>de3750351c0de35472299506ace61a01f2bfc567</id>
<content type='text'>
Pull irq update from Thomas Gleixner:
 "A small set of updats/fixes for the irq subsystem:

   - Allow GICv3 interrupts to be configured as wake-up sources to
     enable wakeup from suspend

   - Make the error handling of the STM32 irqchip init function work

   - A set of small cleanups and improvements"

* 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  irqchip/gic-v3: Allow interrupt to be configured as wake-up sources
  irqchip/tango: Set irq handler and data in one go
  dt-bindings: irqchip: renesas-irqc: Document r8a774a1 support
  irqchip/s3c24xx: Remove unneeded comparison of unsigned long to 0
  irqchip/stm32: Fix init error handling
  irqchip/bcm7038-l1: Hide cpu offline callback when building for !SMP
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Pull irq update from Thomas Gleixner:
 "A small set of updats/fixes for the irq subsystem:

   - Allow GICv3 interrupts to be configured as wake-up sources to
     enable wakeup from suspend

   - Make the error handling of the STM32 irqchip init function work

   - A set of small cleanups and improvements"

* 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  irqchip/gic-v3: Allow interrupt to be configured as wake-up sources
  irqchip/tango: Set irq handler and data in one go
  dt-bindings: irqchip: renesas-irqc: Document r8a774a1 support
  irqchip/s3c24xx: Remove unneeded comparison of unsigned long to 0
  irqchip/stm32: Fix init error handling
  irqchip/bcm7038-l1: Hide cpu offline callback when building for !SMP
</pre>
</div>
</content>
</entry>
</feed>
