linux-stable.git/Documentation/devicetree/bindings/dma, branch linux-rolling-stable

dt-bindings: dma: snps,dw-axi-dmac: Add fallback compatible for CV1800B

2026-07-24T14:20:12+00:00

[ Upstream commit 7524fe142b5a772f8421aeee2132cf7e21a00103 ]

The previous version of the binding change only add compatible
string without adding the fallback compatible, this breaks
backward compatibility. Add the needed fallback compatible to
fix this.

Fixes: be3e2a0419c6 ("dt-bindings: dma: snps,dw-axi-dmac: Add CV1800B compatible")
Signed-off-by: Inochi Amaoto 
Acked-by: Conor Dooley 
Link: https://patch.msgid.link/20260511063818.463877-2-inochiama@gmail.com
Signed-off-by: Vinod Koul 
Signed-off-by: Sasha Levin

dt-bindings: dma: nvidia,tegra186-gpc-dma: Make reset optional

2026-07-24T14:20:04+00:00

[ Upstream commit cc6049bd3fa8501ee27042df469a19ed69cf406d ]

On Tegra264, GPCDMA reset control is not exposed to Linux and is handled
by the boot firmware.

Although reset was not exposed in Tegra234 as well, the firmware supported
a dummy reset which just returns success on reset without doing an actual
reset. This is also not supported in Tegra264 BPMP. Therefore mark 'reset'
and 'reset-names' properties as required only for devices prior to
Tegra264.

This also necessitates that the Tegra264 compatible be standalone and
cannot have the fallback compatible of Tegra186. Since there is no
functional impact, we keep reset as required for Tegra234 to avoid
breaking the ABI.

Fixes: bb8c97571db5 ("dt-bindings: dma: Add Tegra264 compatible string")
Signed-off-by: Akhil R 
Acked-by: Rob Herring (Arm) 
Acked-by: Thierry Reding 
Reviewed-by: Jon Hunter 
Link: https://patch.msgid.link/20260331102303.33181-2-akhilrajeev@nvidia.com
Signed-off-by: Vinod Koul 
Signed-off-by: Sasha Levin

dt-bindings: dmaengine: Fix spelling mistake "Looongson" -> "Looogson"

2026-03-18T09:41:15+00:00

There is a spelling mistake in the title field. Fix it.

Signed-off-by: Colin Ian King 
Reviewed-by: Binbin Zhou 
Link: https://patch.msgid.link/20260317204938.120729-1-colin.i.king@gmail.com
Signed-off-by: Vinod Koul

dt-bindings: dmaengine: Add Loongson Multi-Channel DMA controller

2026-03-17T11:18:55+00:00

The Loongson-2K0300/Loongson-2K3000 have built-in multi-channel DMA
controllers, which are similar except for some of the register offsets
and number of channels.

Obviously, this is quite different from the APB DMA controller used in
the Loongson-2K0500/Loongson-2K1000, such as the latter being a
single-channel DMA controller.

To avoid cluttering a single dt-binding file, add a new yaml file.

Reviewed-by: Rob Herring (Arm) 
Signed-off-by: Binbin Zhou 
Reviewed-by: Huacai Chen 
Link: https://patch.msgid.link/135802de72b84f643d0b0624f3f79f13777147a1.1772853681.git.zhoubinbin@loongson.cn
Signed-off-by: Vinod Koul

dt-bindings: dma: xlnx,axi-dma: Convert to DT schema

2026-03-17T10:56:24+00:00

Convert the bindings document for Xilinx DMA.
No changes to existing binding description.

Signed-off-by: Abin Joseph 
Reviewed-by: Rob Herring (Arm) 
Link: https://patch.msgid.link/20260309033444.3472359-1-abin.joseph@amd.com
Signed-off-by: Vinod Koul

dt-bindings: dma: rz-dmac: Add conditional schema for RZ/G3L

2026-03-17T10:55:56+00:00

The RZ/G3L DMA controller is compatible with RZ/G2L, sharing the same
IP. However, the conditional schema logic that enforces RZ/G2L-specific
binding constraints was not extended to cover the RZ/G3L compatible
string, leaving its bindings without proper validation.

Add the RZ/G3L compatible string to the existing RZ/G2L conditional
schema so that the same property constraints are applied to both SoCs.

Signed-off-by: Biju Das 
Fixes: e45cf0c7d9b960f1 ("dt-bindings: dma: rz-dmac: Document RZ/G3L SoC")
Reviewed-by: Geert Uytterhoeven 
Acked-by: Rob Herring (Arm) 
Link: https://patch.msgid.link/20260306145819.897047-1-biju.das.jz@bp.renesas.com
Signed-off-by: Vinod Koul

dt-bindings: dma: renesas,rz-dmac: document RZ/{T2H,N2H}

2026-03-09T11:26:30+00:00

The Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs have three
DMAC instances. Compared to the previously supported RZ/V2H, these SoCs
are missing the error interrupt line and the reset lines, and they use
a different ICU IP.

Document them, and use RZ/T2H as a fallback for RZ/N2H as the DMACs are
entirely compatible.

Signed-off-by: Cosmin Tanislav 
Reviewed-by: Rob Herring (Arm) 
Reviewed-by: Geert Uytterhoeven 
Link: https://patch.msgid.link/20260105114445.878262-4-cosmin-gabriel.tanislav.xa@renesas.com
Signed-off-by: Vinod Koul

dt-bindings: dma: snps,dw-axi-dmac: Add CV1800B compatible

2026-02-26T15:30:01+00:00

The DMA controller on CV1800B needs to use the DMA phandle args
as the channel number instead of hardware handshake number, so
add a new compatible for the DMA controller on CV1800B.

Signed-off-by: Inochi Amaoto 
Acked-by: Conor Dooley 
Link: https://patch.msgid.link/20260120013706.436742-2-inochiama@gmail.com
Signed-off-by: Vinod Koul

dt-bindings: dma: snps,dw-axi-dmac: add dma-coherent property

2026-02-25T09:59:53+00:00

The Synopsys DesignWare AXI DMA Controller on Agilex5, the controller
operates on a cache-coherent AXI interface, where DMA transactions are
automatically kept coherent with the CPU caches. In previous generations
SoC (Stratix10 and Agilex) the interconnect was non-coherent, hence there
is no need for dma-coherent property to be presence. In Agilex 5, the
architecture has changed. It  introduced a coherent interconnect that
supports cache-coherent DMA.

Signed-off-by: Khairul Anuar Romli 
Reviewed-by: Rob Herring (Arm) 
Signed-off-by: Dinh Nguyen 
Link: https://patch.msgid.link/20260131172856.29227-1-dinguyen@kernel.org
Signed-off-by: Vinod Koul

dt-bindings: dma: rz-dmac: Document RZ/G3L SoC

2026-02-25T09:58:56+00:00

Document the Renesas RZ/G3L DMAC block. This is identical to the one found
on the RZ/G3S SoC.

Reviewed-by: Fabrizio Castro 
Acked-by: Conor Dooley 
Signed-off-by: Biju Das 
Link: https://patch.msgid.link/20260203103031.247435-2-biju.das.jz@bp.renesas.com
Signed-off-by: Vinod Koul